DP83907 datasheet(10/70 Pages) NSC

10 / 70 page

40 Functional Description (Continued)

TLF12082 – 5

FIGURE 2 IO Port

The DP83907’s internal memory map is accessed one byte

or word at a time via a port within the systems IO space

DP83907 is programmed by the user to control the transfers

between its internal memory and the IO port

The

DP83907’s internal registers and the memory access port

are accessed within the system’s IO map The address

within this IO map is set by Configuration Register A

16-BIT IO PORT COMPATIBLE MODE IO ADDRESS

MAPPING

This mode is compatible with Novell’s NE2000 Architecture

The base IO address of DP83907 is configured by Configu-

ration Register A (either upon power up or by software writ-

ing to this register) At the base IO address the following

stwcture appears

Base a 00h

DP8390

Core

Base a 0Fh

Base a 10h

Data Transfer

Base a17h

Port

Base a 18h

Reset Port

Base a 1Fh

FIGURE 3 IO Port Mode Register IO Map

The DP83907 register space within this area are 8 bits wide

but the data transfer port is 16 bits wide The DP83907’s

registers can be programmed to control the passing of data

between its internal memory and the data transfer port By

accessing the data transfer port (using IO instructions) the

user can transfer data to or from the DP83907’s internal

memory The DP83907’s internal memory map is as shown

below

0000h

D15

001Fh

PROM

Aliased PROM

4000h

8kx16

7FFFh

Buffer RAM

8000h

Aliased PROM

C000h

Aliased

Buffer RAM

FFFh

(a)

D15

001Eh

57h

001Ch

57h

RESERVED

00Ah

E’net Address 5

0008h

E’net Address 4

0006h

E’net Address 3

0004h

E’net Address 2

0002h

E’net Address 1

0000h

E’net Address 0

(b)

FIGURE 4 a) NIC Core’s 16-Bit Memory Map

b) 16-Bit PROM Map

DP83907 has a 64k address range but only does partial

decoding through this space The PROM data is mirrored

from all decodes up to 4000H and the entire map is repeat-

ed at 8000H To access either the PROM or the RAM the

user must initiate a Remote DMA transfer between the IO

port and memory

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