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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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DP83907 датащи(PDF) 57 Page - National Semiconductor (TI) |
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DP83907 датащи(HTML) 57 Page - National Semiconductor (TI) |
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57 / 70 page  60 Operation of DP83907 (Continued) Boot PROM Write Bus Timing TLF12082 – 41 This is the type of cycle used to write to the boot PROM These accesses are entirely asynchronous with the DP83907 responding when it decodes the correct address on SA0-19 and a SMWR If AEN is high the cycle will be ignored CHRDY is deasserted if the DP83907 is not ready to respond and asserted when ready If it is ready immediately CHRDY is not deasserted The data will normally be taken from SD0-7 However if M16 is generated and the access is to an odd address the data will be taken from SD8-15 The data will always be driven onto MSD0-7 The BPWR bit of Configuration Register B must be high to allow write cycles to the boot PROM 57 |
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