TUSB3410 datasheet(25/92 Pages) TI

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4–5

Table 4–3. Memory Mapped Registers Summary (XDATA Range = FF80

→ FFFF) (Continued)

ADDRESS

DESCRIPTION

↑

FF93

RESERVED

WDCSR

Watchdog timer control and status register

FF92

VECINT

Vector interrupt register

↑

RESERVED

FF90

ROMS

ROM shadow configuration register

↑

RESERVED

FF83

OEPBCNT_0

Output endpoint_0: Byte count register

FF82

OEPCNFG_0

Output endpoint_0: Configuration register

FF81

IEPBCNT_0

Input endpoint_0: Byte count register

FF80

IEPCNFG_0

Input endpoint_0: Configuration register

Table 4–4. EDB Memory Locations

ADDRESS

DESCRIPTION

↑

RESERVED

FF58

IEPCNF_3

Input endpoint_3: Configuration

FF50

IEPCNF_2

Input endpoint_2: Configuration

FF48

IEPCNF_1

Input endpoint_1: Configuration

FF47

↑

RESERVED

FF20

FF18

OEPCNF_3

Output endpoint_3: Configuration

FF10

OEPCNF_2

Output endpoint_2: Configuration

FF08

OEPCNF_1

Output endpoint_1: Configuration

FF07

↑

(8 bytes)

Setup packet block

FF00

FEFF

↑

(8 bytes)

Input endpoint-0 buffer

FEF8

FEF7

↑

(8 bytes)

Output endpoint-0 buffer

FEF0

FEEF

TOPBUFF

Top of buffer space

↑

Buffer space

↑

F800

STABUFF

Start of buffer space

4.3

Endpoint Descriptor Block (EDB–1 to EDB–3)

Data transfers between the USB, the MCU, and external devices that are defined by an endpoint descriptor Block

(EDB). Three input- and three output-EDBs are provided. With the exception of EDB–0 (I/O endpoint–0), all EDBs

are located in SRAM as per Table 4–3. Each EDB contains information describing the X- and Y-buffers. In addition,

each EDB provides general status information.

Table 4–5 illustrates the EDB entries for EDB–1 to EDB–3. EDB–0 registers are described separately.

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