TUSB3410 datasheet(49/92 Pages) TI

49 / 92 page

7–3

7.1.4

FCRL: UART Flow Control Register (Addr:FFA3)

This register provides the flow-control modes of operation (see Table 7–3 for more details).

765

485E

DTR

RTS

RXOF

DSR

CTS

TXOA

TXOF

R/W

BIT

NAME

RESET

FUNCTION

TXOF

This bit controls the transmitter Xon/Xoff flow control.

TXOF = 0

TXOF = 1

Disable transmitter Xon/Xoff flow control

Enable transmitter Xon/Xoff flow control

TXOA

This bit controls the transmitter Xon-on-any/Xoff flow control

TXOA = 0

TXOA = 1

Disable the transmitter Xon-on-any/Xoff flow control

Enable the transmitter Xon-on-any/Xoff flow control

CTS

Transmitter CTS flow-control enable bit

CTS = 0

CTS = 1

Disables transmitter CTS flow control

CTS flow control is enabled, i.e., when CTS input pin is high, transmission is halted; when the CTS

pin is low, transmission resumes.

DSR

Transmitter DSR flow-control enable bit

DSR = 0

DSR = 1

Disables transmitter DSR flow control

DSR flow control is enabled, i.e., when DSR input pin is high, transmission is halted; when the DSR

pin is low, transmission resumes.

RXOF

This bit controls the receiver Xon/Xoff flow control.

RXOF = 0

RXOF = 1

Receiver does not attempt to match Xon/Xoff characters

Receiver searches for Xon/Xoff characters

RTS

Receiver RTS flow control enable bit

RTS = 0

RTS = 1

Disables receiver RTS flow control

Receiver RTS flow control is enabled. RTS output pin goes high when the receiver FIFO HALT

trigger level is reached; it goes low, when the receiver FIFO RESUME receiving trigger level is

reached.

DTR

Receiver DTR flow-control enable bit

DTR = 0

DTR = 1

Disables receiver DTR flow control

Receiver DTR flow control is enabled. DTR output pin goes high when the receiver FIFO HALT

trigger level is reached; it goes low, when the receiver FIFO RESUME receiving trigger level is

reached.

485E

RS485 enable bit. This bit is used to configure the UART to control external RS485 transceivers. When

configured in half-duplex mode (485E=1), RTS or DTR can be used to enable the RS485 driver or receiver.

See Figure 5.

485E = 0

485E = 1

UART is in normal operation mode (full duplex)

The UART is in half duplex RS485 mode. In this mode RTS and DTR are active with opposite

polarity (when RTS = 0, DTR = 1). When the DMA is ready to transmit, it drives RTS = 1 (and

DTR = 0) 2–bit–time before transmission starts. When DMA terminates the transmission, it drives

RTS = 0 (and DTR = 1) after transmission stops. When 485E is set to 1, the DTR and RTS bits in

the MCR register have no effect. Also, see the RCVE bit in MCR: modem-control register.

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