TUSB3410 datasheet(41/92 Pages) TI

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6–1

6 DMA Controller

Table 6–1 outlines the DMA channels and their associated transfer directions. Two channels are provided for data

transfer between the host and the UART.

Table 6–1. DMA Controller Registers

DMA CHANNEL

TRANSFER DIRECTION

COMMENTS

DMA–1

Host to UART

DMA writes to UART TDR register

DMA–3

UART to host

DMA reads from UART RDR register

6.1

DMA Controller Registers

Each DMA channel can point to one of three EDBs (EDB[3:1]) and transfer data to/from the UART channel. The DMA

can move data from a given out-point buffer (defined by EDB) to the destination port. Similarly, the DMA can move

data from a port to a given input-endpoint buffer. Two modes of DMA transfers are supported: burst and continuous.

•

Burst (CNT = 0) Mode

The DMA stops at the end of a block-data transfer (or if an error condition occurred) and interrupts the MCU.

It is the responsibility of the MCU to update the X/Y bit and the NAK bit in the EDB.

•

Continuous (CNT = 1) Mode

At the end of a block transfer the DMA updates the byte count and NAK bit in the EDB when receiving. In

addition, it uses the X/Y bit to switch automatically, without interrupting the MCU (the X/Y bit toggle is

performed by the UBM). The DMA stops only when a time-out or error condition occurs. When the DMA is

transmitting (from the X/Y buffer) it continues alternating between X/Y buffers until it detects a byte count

smaller than the buffer size (buffer size is typically 64 bytes). At that point it completes the transfer and stops.

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