TUSB3410 datasheet(51/92 Pages) TI

51 / 92 page

7–5

7.1.6

MCR: Modem-Control Register (Addr:FFA4)

This register provides control for modem interface I/O and definition of the flow control mode.

765

LCD

LRI

RTS

DTR

SEN

LOOP

RCVE

URST

R/W

BIT

NAME

RESET

FUNCTION

URST

Uart soft reset. This bit can be used by the MCU to reset the UART.

URST = 0

Normal operation. Writing a 0 by MCU has no effect.

URST = 1

When the MCU writes a 1 to this bit, a UART reset is generated (ORed with hard reset). When

the UART exits the reset state, URST is cleared. The MCU can monitor this bit to determine if the

UART completed the reset cycle.

RCVE

Receiver enable bit. This bit is valid only when 485E in FCRL is 1 (RS485 mode). When 485E = 0, this bit has

no effect on the receiver.

RCVE = 0

When 485E = 1, the UART receiver is disabled when RTS = 1, i.e., when data is being transmitted,

the UART receiver is disabled.

RCVE = 1

When 485E = 1, the UART receiver is enabled regardless of the RTS state, i.e., UART receiver

is enabled all the time. This mode can be used to detect collisions on the RS-485 bus when

received data does not match transmitted data.

LOOP

This bit controls the normal-/loop-back mode of operation (see Figure 7–1).

LOOP = 0

Normal operation

LOOP = 1

Enable loop-back mode of operation. In this mode the following occur:

SOUT is set high

SIN is disconnected from the receiver input.

The transmitter serial output is looped back into the receiver serial input.

The four modem-control inputs: CTS, DSR, DCD, and RI are disconnected.

DTR, RTS, LRI and LCD are internally connected to the four modem-control inputs, and read

in the MSR register as follows:

S DTR is reflected in MSR[4] bit

S RTS is reflected in MSR[5] bit

S LRI is reflected in MSR[6] bit

S LCD is reflected in MSR[7] bit

RSV

Reserved

DTR

This bit controls the state of the DTR output pin (see Figure 7–1). This bit has no effect when auto-flow control

is used or when 485E = 1 (in FCRL register).

DTR = 0

Forces the DTR output pin to inactive (high)

DTR = 1

Forces the DTR output pin to active (low)

RTS

This bit controls the state of the RTS output pin (see Figure 7–1). This bit has no effect when auto-flow control

is used or when 485E = 1 (in FCRL register).

RTS = 0

Forces the RTS output pin to inactive (high)

RTS = 1

Forces the RTS output pin to active (low)

TUSB3410 датащи(PDF) 51 Page - Texas Instruments

TUSB3410 датащи(HTML) 51 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92

датащи скачать

ссылки URL