TUSB3410 datasheet(45/92 Pages) TI

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6–5

6.1.4

DMACSR3: DMA Control And Status Register (UART Receive Channel) (Addr:FFE5)

This register is used to define the transaction time-out value. In addition, it contains a completion code that reports

any errors or a time-out condition.

765

TEN

TXFT

OVRUN

R/W

R/C

BIT

NAME

RESET

FUNCTION

OVRUN

Overrun condition bit. This bit is set by DMA and cleared by the MCU (see Table 6–3)

OVRUN = 0

No overrun condition

OVRUN = 1

Overrun condition detected. When IEN = 0, this bit does not clear the EN bit in DMACDR;

therefore, the DMAC stays enabled, ready for the next transaction. Clears when the MCU writes

a 1. Writing a 0 has no effect.

TXFT

Transfer time-out condition bit (see Table 6–3)

TXFT = 0

DMA stopped transfer without time-out

TXFT =1

DMA stopped due to transaction time-out. When IEN = 0, this bit does not clear the EN bit in

DMACDR; therefore, the DMAC stays enabled, ready for the next transaction. Clears when the

MCU writes a 1. Writing a 0 has no effect.

6–2

C[4:0]

00000b

This field is used to define the transaction time-out value in 1-ms increments. This value is loaded to a down

counter every time a byte transfer occurs. The down counter is decremented every SOF pulse (1 ms). If the

counter decrements to zero it sets TXFT = 1 (in DMACSR register) and halts the DMA transfer. The counter starts

counting only when TEN = 1 and EN = 1 (in DMACDR) and the first byte has been received (see Figure 6–1).

00000 = 0-ms time-out

11111 = 31-ms time-out

TEN

Transaction time-out counter enable/disable bit

TEN = 0

TEN = 1

Counter is disabled (does not time-out)

Counter is enabled

Table 6–3. DMA IN-Termination Condition

IN TERMINATION

TXFT

OVRUN

COMMENTS

UART error

UART error condition detected

UART partial packet

This condition occurs when UART receiver has no more data for the host (data

starvation).

UART overrun

This condition occurs when X- and Y-input buffers are full and the UART FIFO is full (host

is busy).

6.2

Bulk Data I/O Using the EDB

The UBM (USB buffer manager) and the DMAC (DMA controller) access the EDB to fetch buffer parameters for IN

and OUT transactions (IN and OUT are with respect to host). In this discussion, it is assumed that (a) the MCU

initialized the EDBs, (b) DMA-continuous mode is being used, (c) double buffering is being used, and (d) the X/Y

toggle is controlled by the UBM.

NOTE: The IN and OUT transfers apply to UART.

6.2.1

IN Transaction (TUSB3410 to Host)

The MCU initializes the IEDB (64-byte packet, and double buffering is used) and the following DMA

registers:

•

DMACSR: Defines the transaction time-out value.

•

DMACDR: Defines the IEDB being used and the DMA mode of operation (continuous mode). Once this

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