TUSB3410 datasheet(52/92 Pages) TI

52 / 92 page

7–6

LRI

This bit is used for loop-back mode only. When in loop-back mode, this bit is reflected in MSR[6]-bit (see

Figure 7–1).

LRI = 0

Clears MSR[6] = 0

LRI = 1

Sets MSR[6] = 1

LCD

This bit is used for loop-back mode only. When in loop-back mode, this bit is reflected in MSR[7]-bit (see

Figure 7–1).

LCD = 0

Clears MSR[7] = 0

LCD = 1

Sets MSR[7] = 1

7.1.7

LSR: Line-status Register (Addr:FFA5)

This register provides the status of the data transfer. DMA transfer is halted when any of OVR, PTE, FRE, BRK, or

EXIT is 1.

765

RSV

TEMT

TxE

RxF

BRK

FRE

PTE

OVR

R/O

R/C

BIT

NAME

RESET

FUNCTION

OVR

This bit indicates the overrun condition of the receiver. If set, it halts the DMA transfer and generates a

status interrupt (if enabled).

OVR = 0

OVR = 1

No overrun error

Overrun error has occurred. Clears when the MCU writes a 1. Writing a 0 has no effect.

PTE

This bit indicates the parity condition of the received byte. If set, it halts the DMA transfer and generates a

status interrupt (if enabled).

PTE = 0

PTE = 1

No parity error in data received

Parity error in data received. Clears when the MCU writes a 1. Writing a 0 has no effect.

FRE

This bit indicates the framing condition of the received byte. If set, it halts the DMA transfer and generates

a status interrupt (if enabled).

FRE = 0

FRE = 1

No framing error in data received

Framing error in data received. Clears when MCU writes a 1. Writing a 0 has no effect.

BRK

This bit indicates the break condition of the received byte. If set, it halts the DMA transfer and generates a

status interrupt (if enabled).

BRK = 0

BRK = 1

No break condition

A break condition in data received was detected. Clears when the MCU writes a 1. Writing a 0

has no effect.

RxF

This bit indicates the condition of the receiver data register. Typically, the MCU does not monitor this bit

since data transfer is done by the DMA controller.

RxF = 0

RxF = 1

No data in the RDR

RDR contains data. Generates Rx interrupt (if enabled).

TxE

This bit indicates the condition of the transmitter data register. Typically, the MCU does not monitor this bit

since data transfer is done by the DMA controller.

TxE = 0

TxE = 1

TDR is not empty

TDR is empty. Generates Tx interrupt (if enabled).

TEMT

This bit indicates the condition of both transmitter data register and shift register is empty.

TEMT = 0

TEMT = 1

Either TDR or TSR is not empty

Both TDR and TSR are empty

RSV

Reserved = 0

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