PM0056 datasheet(132/156 Pages) STMICROELECTRONICS

132 / 156 page

Core peripherals

PM0056

132/156

DocID15491 Rev 5

Bit 31

NMIPENDSET: NMI set-pending bit.

Write:

0: No effect

1: Change NMI exception state to pending.

Read:

0: NMI exception is not pending

1: NMI exception is pending

Because NMI is the highest-priority exception, normally the processor enter the NMI

exception handler as soon as it registers a write of 1 to this bit, and entering the handler clears

this bit to 0. A read of this bit by the NMI exception handler returns 1 only if the NMI signal is

reasserted while the processor is executing that handler.

Bits 30:29

Reserved, must be kept cleared

Bit 28

PENDSVSET: PendSV set-pending bit.

Write:

0: No effect

1: Change PendSV exception state to pending.

Read:

0: PendSV exception is not pending

1: PendSV exception is pending

Writing 1 to this bit is the only way to set the PendSV exception state to pending.

Bit 27

PENDSVCLR: PendSV clear-pending bit.

Write:

0: No effect

1: Removes the pending state from the PendSV exception.

Bit 26

PENDSTSET: SysTick exception set-pending bit.

Write:

0: No effect

1: Change SysTick exception state to pending

Read:

0: SysTick exception is not pending

1: SysTick exception is pending

Bit 25

PENDSTCLR: SysTick exception clear-pending bit.

Write:

0: No effect

1: Removes the pending state from the SysTick exception.

This bit is write-only. On a register read its value is unknown.

Bit 24

Reserved, must be kept cleared.

Bit 23

This bit is reserved for Debug use and reads-as-zero when the processor is not in Debug.

Bit 22

ISRPENDING: Interrupt pending flag, excluding NMI and Faults

0: Interrupt not pending

1: Interrupt pending

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