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AN4192 датащи(PDF) 41 Page - STMicroelectronics |
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AN4192 датащи(HTML) 41 Page - STMicroelectronics |
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41 / 47 page ![]() AN4192 Low-side FET selection Doc ID 023820 Rev 1 41/47 Figure 51. RG,HS(EXT) = 2.2 Ω - RG,HS(EXT) = 1.8 Ω/ RSNUB = 1 Ω waveforms @ 20 A Therefore, the last configuration is the best in terms of phase node ringing smoothing (12%, from 33.6 V to 29. 6 V, see Figure 52). The increased LS gate resistor value (1.8 Ω) doesn't negatively effect the LS gate-source bouncing and the potential shoot-through risks: this spurious voltage is higher than VTH,min (1 V) for only 1.7 ns; it is not enough to charge the MOSFET input capacitance and turn-on of the device itself. Figure 52. Phase node improvement AM16494V1 AM16495V1 |
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