AN4192 datasheet(12/47 Pages) STMICROELECTRONICS

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High-side MOSFET selection

AN4192

12/47

Doc ID 023820 Rev 1

At fSW = 300 kHz, the different “switching charge” values don't strongly affect the efficiency

curves (1.2% efficiency improvement of “high-side 2” vs. “high-side 4”). But, if we step up

the switching frequency to 440 kHz, the HS FET with the lowest QG,SW (“high-side 2”) has

the best efficiency in the overall current range, due to the switching losses reduction.

Then, high-side FETs with very low QG,SW make the design more efficient and are the best

solution in high frequency VRM applications.

2.0.2

QG,SW impact on the HS switching behavior

QG,SW, particularly QGD, also affects the high-side switching behavior during turn-on and

turn-off. Referring to the gate charge image (Figure 4), during the “Miller plateau” (from t1 to

t2) the MOSFET works in the active region (VDS > VDS,SAT), so the gate-source voltage is

constant while the drain current is the full load current. In this time interval, the MOSFET

drain-source voltage drops from high level to zero (at turn-on) or rises from zero to high level

(at turn-off) (see Figure 8). Since CGS is fully charged, the gate current flows only through

CGD, so there is a strong relationship between VDS falling edge slope and QGD:

Equation 2

IG is the total gate charging current. The bigger the Miller capacitance, the lower the VDS

slope, and vice versa.

Figure 8.

MOSFET equivalent circuit during Miller plateau

In order to show the CGD impact on the HS switching performance, two 30 V FETs (MOS1,

CGD = 76 pF @ 25 V and MOS2, CGD = 150 pF @ 25 V) are compared as high-side FETs in

a two-phase synchronous buck converter (VIN = 12 V, VOUT = 1.5 V, IOUT = 44 A, 1 x HS, 2 x

LS, fSW = 440 kHz). External HS and LS gate resistances are present in the layout (RG,HS =

2.2

Ω, RG,LS = 2.2 Ω), whereas no RC snubber network is used.

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AM16452V1

AN4192 датащи(PDF) 12 Page - STMicroelectronics