AN4192 datasheet(35/47 Pages) STMICROELECTRONICS

номер детали	AN4192

подробное описание детали	In the latest generation of CPUs for modern desktop and notebook platforms

PDF	47 Pages

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производитель	STMICROELECTRONICS [STMicroelectronics]

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35 / 47 page

AN4192

Low-side FET selection

Doc ID 023820 Rev 1

35/47

strongest smoothing effect. Another important phenomenon that affects the LS switching

performance is the LS gate-source spurious oscillations. When the HS turns on, spurious

ringing appears between LS gate and source, caused by high dVphase/dt and the parasitic

effects due to the PCB stray inductances (at all the MOSFET pins).

Figure 42.

Simplified LS FET circuit

To reduce the phase node spike and therefore LS gate-source parasitic fluctuations, the

“filter effect” provided by the MOSFET intrinsic output capacitance (COSS = CGD + CDS) is

important. In fact, COSS works as an “intrinsic” capacitive snubber between drain and

source.

Figure 43.

Single-phase synchronous buck converter schematic

In a single-phase buck converter demonstration board (VIN = 12 V, VOUT = 1.25 V, fSW = 270

kHz, 1 x HS, 1 x LS, IOUT = 20 A, Figure 43), the benefits given by two paralleled 30 V FETs

(doubled Cgs) in terms of LS G-S induced ringing are evaluated. External gate resistances

are connected to HS (2.2

Ω) and LS (2.2 Ω) FETs. An RC snubber network (CSNUB = 6.8 nF,

RSNUB = 1.8 Ω) is used to improve the switching behavior. As shown in Figure 44 (purple

trace: 2 x LS - yellow trace: 1 x LS), the two paralleled LS FETs have smoothed high

frequency LS oscillations, both in the highest and in the lowest spike.

AM16485V1

AM16486V1

AN4192 датащи(PDF) 35 Page - STMicroelectronics