AN4192 datasheet(20/47 Pages) STMICROELECTRONICS

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Low-side FET selection

AN4192

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Doc ID 023820 Rev 1

Low-side FET selection

The low-side FET performance can be enhanced by properly choosing the following

MOSFET electrical parameters:

RDS(on) (ON-state drain-source resistance): as the LS FET is in the ON-state for a

longer time, the conduction losses, strictly related to the RDS(on) value, are the most

important power dissipation contribution. Based on the converter layout and the output

current requirements, one or more paralleled LS FETs can be used.

CGD (Miller capacitance): it affects the LS switching behavior, in terms of phase node

spike and dVphase/dt. On the other hand, too high CGD values increase the LS

“switching charge” (QG,SW): in high frequency applications or when more LS FETs are

paralleled to reduce the RDSon, this may increase the switching and gate drive losses,

even if the LS switches at nearly ZVS (due to its body diode conduction).

QRR (LS body-drain diode reverse recovery charge): during the deadtime (when the HS

and LS are in the HOLD state), the load current flows through the body-drain diode

(forward biased). When the HS turns on, the excess charge stored in the LS body diode

(QRR) must be removed before the phase node turns high.

RG (external and intrinsic gate resistance): when no additional smoothing effects are

present (i.e. snubber network), the higher the RG, the lower the Vphase,max. The

drawback is the LS G-S spurious ringing that may induce the LS spurious turn-on

again.

Furthermore, the LS FET performance is also influenced by the RC snubber network

setting, connected between LS drain and source, which helps to smooth the phase node

noise. Another important aspect is the spurious LS gate-source bouncing, induced by the

fast rising edge of the phase node through the Miller capacitance; it is analyzed with a

particular focus on the different solutions to reduce these parasitic oscillations. Finally, the

converter output voltage (and the converter duty cycle) affects the phase node noise

behavior: the higher the VOUT, the lower the phase node overshoot, during the HS turn-on.

3.1

RDS(on) and conduction losses minimization

The LS conduction losses are given by:

Equation 4

As the converter duty cycle (for typical VRM applications) is very low (0.1 - 0.2%), the LS

FET is in the ON-state for a longer time: the conduction losses are the most important power

dissipation term. The RDS(on) minimization is crucial for the optimization of the LS

performance. Bigger die sizes are preferred, even though the device cost is a constraint. If

the output current to be delivered to the load is high, more LS can be used in parallel.

To better understand the impact of the RDS(on) on the converter efficiency, two LS FETs are

compared in a 3-phase buck converter (VIN = 12 V, VOUT = 1.25 V, fSW = 300 kHz, 2 x HS, 2

x LS, IOUT = 75 A; see Figure 21). External gate resistances are connected to HS (2.2 Ω)

and LS (2.2

Ω) FETs. An RC snubber network (RSNUB = 2.2 Ω, CSNUB = 4.7 nF) is used to

smooth the phase node.

COND,LS

DS on

() TID

–

()

⋅⋅

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