AN4192 datasheet(22/47 Pages) STMICROELECTRONICS

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Low-side FET selection

AN4192

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Doc ID 023820 Rev 1

Figure 22.

Buck converter schematic

When the HS turns on (the load current is I1), the phase node goes from low to high level in

a few nanoseconds: depending on several factors, an overvoltage (plus high frequency

oscillations) event may appear on the LS drain-source voltage (phase node ringing): if the

maximum spike is higher than the breakdown voltage (BVDSS), the MOSFET safety and

reliability can worsen. This issue is related to three main factors:

When the HS turns on, VDS,LS rises from -0.7 V (body-drain diode conduction) to

supply voltage. If the HS switches sharply (very low QG,SW), high dVDS,LS/dt and phase

node spike is measured on the LS FET.

During the deadtime, when the load current flows through the LS body-drain diode,

parasitic voltage drops (VL1 and VL2) appear across the PCB stray inductances

(connected to LS drain and source, Figure 23). So, the parasitic voltage drops, and VL1

and VL2 increase the VDS,LS maximum value, creating potential issues for MOSFET

safety and reliability, if the maximum spike is higher than the BVDSS guaranteed in the

datasheet.

During the deadtime, the LS body-drain diode is forward biased (VDS,LS = -0.7 V). This

excess stored charge must be removed before the LS can sustain the supply voltage; in

order to reverse bias the body diode, a “reverse recovery current” flows (from drain to

source) immediately after the HS turn-on. The larger this current is, the higher the

phase node spike is. In the next section, there is a more thorough analysis of the

benefits given by a “soft” LS body-drain diode.

Figure 23.

Impact of the stray inductances on the phase node ringing

AM16466V1

AM16467V1

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