AN4192 datasheet(30/47 Pages) STMICROELECTRONICS

30 / 47 page

Low-side FET selection

AN4192

30/47

Doc ID 023820 Rev 1

3.4

RG and LS gate-source bouncing

Now, the impact of the intrinsic and external gate resistances on the overall converter

behavior is analyzed.

The intrinsic gate resistance of a MOSFET mainly affects its switching speed and

consequently the switching losses. So, for a HS FET, it is mandatory to have a total gate

resistance (RG,HS(EXT) + RG,HS(INT)) not too big in order to diminish the HS switching losses

(major losses contribution), particularly at high fSW.

On the other hand, the LS FET turns on and off with nearly zero voltage drop across it

(because, before its turn-on and after turn-off, the current flows through the LS body-drain

diode, so VDS,LS = -0.7 V); therefore, the switching losses are not comparable to the

conduction ones. The right RG value should be chosen considering the trade-off between

phase node spike smoothing (high RG) and CdV/dt spurious turn-on immunity (low RG). In

fact, when the HS turns on, a high dVphase/dt appears across the LS device (its value

depends also on the HS switching speed).

Figure 34.

LS FET during HS turn-on

A capacitive current flows through the Miller capacitance (Cgd):

Equation 6

During the OFF-state, the LS gate is pulled down to GND through the driver sink resistance

(RDRV). So, if RDRV + RG,LS(EXT) + RG,LS(INT) << Zgs, most of the capacitive current flows in

the resistive path towards GND. As a consequence, a “spurious” voltage drop appears

between LS gate and source:

Equation 7

If Vgs,LS is higher than the LS threshold voltage, the FET may turn on, creating a low-

impedance path, between phase node and GND. There is a potential risk of a “cross-

conduction” (or shoot-through) event, because the HS is turned on and a low impedance

path between VDD and GND exists.

AM16477V1

phase

----------------------

⋅

gs,LS

DRV

G,LS(EXT)

G,LS(INT)

() C

phase

----------------------

⋅⋅

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