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AN4192 датащи(PDF) 33 Page - STMicroelectronics |
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AN4192 датащи(HTML) 33 Page - STMicroelectronics |
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33 / 47 page ![]() AN4192 Low-side FET selection Doc ID 023820 Rev 1 33/47 Figure 39. 2-phase synchronous buck converter In a 2-phase synchronous buck converter (Figure 39) (VIN = 12 V, VOUT = 1.5 V, IOUT = 44 A, 1 x HS, 2 x LS, fSW = 440 kHz), two LS FETs with different RG,INT values (RG1 = 1.3 Ω, RG2 = 2.8 Ω) are compared. External HS and LS gate resistances are present in the layout (RG,HS = 2.2 Ω, RG,LS = 2.2 Ω). Higher intrinsic gate resistance is helpful to smooth the phase node overshoot, when no RC snubber network is connected in parallel to the LS FET. In Figure 40 and 41 the phase node waveforms of the two LS FETs tested at full load conditions (IOUT = 44 A) are compared. AM16482V1 |
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