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ADE7754

INTERRUPTS

ADE7754 interrupts are managed through the interrupt status

occurs in the ADE7754, the corresponding flag in the interrupt

status register is set to Logic 1. See the Interrupt Status Register

section. If the enable bit for this interrupt in the interrupt enable

IRQ logic output goes active low.

The flag bits in the interrupt status register are set irrespective

of the state of the enable bits. In order to determine the source

of the interrupt, the system master (MCU) should perform a

read from the reset interrupt status register with reset. This is

achieved by carrying out a read from Address 11h. The

IRQ

output goes logic high on completion of the interrupt status

carrying out a read with reset, the ADE7754 is designed to

ensure that no interrupt events are missed. If an interrupt event

occurs just as the interrupt status register is being read, the

event will not be lost and the

IRQ logic output is guaranteed to

go high for the duration of the interrupt status register data

transfer before going logic low again to indicate the pending

interrupt.

Using Interrupts with an MCU

The timing diagram in Figure 47 illustrates a suggested imple-

mentation of ADE7754 interrupt management using an MCU.

At time t1, the IRQ line goes active low indicating that one or

more interrupt events have occurred. The

IRQ logic output

should be tied to a negative edge triggered external interrupt on

the MCU. On detection of the negative edge, the MCU should

be configured to start executing its interrupt service routine

(ISR). On entering the ISR, all interrupts should be disabled

using the global interrupt enable bit. At this point the MCU

external interrupt flag can be cleared in order to capture inter-

rupt events that occur during the current ISR. When the MCU

interrupt flag is cleared, a read from the reset interrupt status

IRQ line to be

reset logic high (t2). See the Interrupt Timing section. The reset

interrupt status register contents are used to determine the

source of the interrupt(s) and therefore the appropriate action to

be taken. If a subsequent interrupt event occurs during the ISR

(t3), that event will be recorded by the MCU external interrupt

flag being set again. On returning from the ISR, the global

interrupt enable bit will be cleared (same instruction cycle) and

the external interrupt flag will cause the MCU to jump to its

ISR once again. This will ensure that the MCU does not miss

any external interrupts.

Interrupt Timing

The Serial Interface section should be reviewed first before

reviewing interrupt timing. As previously described, when the

IRQ output goes low, the MCU ISR must read the interrupt

status register in order to determine the source of the interrupt.

When reading the interrupt status register contents, the

IRQ

output is set high on the last falling edge of SCLK of the first

byte transfer (read interrupt status register command). The

IRQ

output is held high until the last bit of the next 8-bit transfer is

shifted out (interrupt status register contents). See Figure 48. If

an interrupt is pending at this time, the

IRQ output will go low

again. If no interrupt is pending, the

IRQ output will remain high.

IRQ

JUMP TO

ISR

GLOBAL

INTERRUPT

MASK

CLEAR MCU

INTERRUPT

FLAG

READ

STATUS WITH

RESET (11h)

ISR ACTION

(BASED ON STATUS CONTENTS)

ISR RETURN

GLOBAL INTERRUPT

MASK RESET

MCU

INT. FLAG SET

JUMP TO

ISR

PROGRAM

SEQUENCE

Figure 47. Interrupt Management

SCLK

DIN

t11

t12

DB15

DOUT

DB8

DB7

READ STATUS REGISTER COMMAND

IRQ

STATUS REGISTER CONTENTS

DB0

Figure 48. Interrupt Timing

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