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ADE7754

SERIAL INTERFACE

ADE7754 has a built-in SPI interface. The serial interface of

the ADE7754 is made of four signals: SCLK, DIN, DOUT,

and

CS. The serial clock for a data transfer is applied at the

SCLK logic input, which has a Schmidt-trigger input structure

that allows slow rising (and falling) clock edges to be used. All

data transfer operations are synchronized to the serial clock.

Data is shifted into the ADE7754 at the DIN logic input on the

falling edge of SCLK. Data is shifted out of the ADE7754 at the

DOUT logic output on a rising edge of SCLK. The

CS logic

input is the chip-select input. This input is used when multiple

devices share the serial bus. A falling edge on

CS also resets the

serial interface and places the ADE7754 into communications

mode. The

CS input should be driven low for the entire data

transfer operation. Bringing

CS high during a data transfer

operation will abort the transfer and place the serial bus in a

high impedance state. The

CS logic input may be tied low if the

ADE7754 is the only device on the serial bus. However, with

CS tied low, all initiated data transfer operations must be fully

completed (i.e., the LSB of each register must be transferred

because there is no other way to bring the ADE7754 back into

communications mode without resetting the entire device,

i.e., setting the

RESET pin logic low).

All the ADE7754 functionality is accessible via several on-chip

registers. See Figure 41. The contents of these registers can be

updated or read using the on-chip serial interface. After power-

on or toggling the

RESET pin low, or a falling edge on CS, the

ADE7754 is placed into communications mode. In communica-

tions mode, the ADE7754 expects the first communication to

be a write to the internal communications register. The data

written to the communications register contains the address and

specifies the next data transfer to be a read or a write command.

Therefore all data transfer operations with the ADE7754,

whether read or write types, must begin with a write to the

communications register.

COMMUNICATIONS REGISTER

DIN

DOUT

OUT

Figure 41. Addressing ADE7754 Registers via the

Communications Register

The communications register is an 8-bit write-only register. The

MSB determines whether the next data transfer operation is a

read or a write. The six LSBs contain the address of the register

to be accessed. See the Communications Register section for a

more detailed description.

Figure 42 and Figure 43 show the data transfer sequences for a

read and write operation, respectively. On completion of a data

transfer (read or write), the ADE7754 once again enters com-

munications mode (i.e., the next instruction followed must be a

write to the communications register).

COMMUNICATIONS REGISTER WRITE

DIN

DOUT

SCLK

0 0

ADDRESS

MULTIBYTE READ DATA

Figure 42. Reading Data from the ADE7754 via the

Serial Interface

1 0

ADDRESS

MULTIBYTE WRITE DATA

COMMUNICATIONS REGISTER WRITE

DIN

SCLK

Figure 43. Writing Data to the ADE7754 via the

Serial Interface

A data transfer is completed when the LSB of the ADE7754

or from the ADE7754.

Serial Write Operation

The serial write sequence requires the following steps. With the

ADE7754 in communications mode and the

CS input logic low,

a write to the communications register takes place. The MSB of

this byte transfer must be set to 1, indicating that the next data

transfer operation is a write to the register. The six LSBs of this

byte contain the address of the register to be written to. The

ADE7754 starts shifting in the register data on the next falling

edge of SCLK. All remaining bits of register data are shifted in

on the falling edge of subsequent SCLK pulses. See Figure 44.

As explained previously, the data write is initiated by a write to

the communications register, followed by the data. During a data

write operation to the ADE7754, data is transferred to all on-chip

registers one byte at a time. After a byte is transferred into the

serial port, there is a finite amount of time before the content of

the serial port buffer is transferred to one of the ADE7754 on-chip

registers. Although another byte transfer to the serial port can

start while the previous byte is being transferred to the destina-

tion register, this second byte transfer should not finish until at

least 1

µs after the end of the previous byte transfer. This func-

tionality is expressed in the timing specification t6. See Figure 44.

If a write operation is aborted during a byte transfer

(CS brought

high), then that byte will not be written to the destination register.

Destination registers may be up to 3 bytes wide. See the Register

Descriptions section. Therefore, the first byte shifted into the

serial port at DIN is transferred to the MSB (most significant

byte) of the destination register. If the destination register is 12 bits

wide, for example, a 2-byte data transfer must take place. The

data is always assumed to be right justified; therefore, in this

case, the four MSBs of the first byte would be ignored and the four

LSBs of the first byte written to the ADE7754 would be the four

MSBs of the 12-bit word. Figure 45 illustrates this example.

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