ADE7754_15 datasheet(14/44 Pages) AD

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ADE7754

VPEAK[7:0]

PKV INTERRUPT

FLAG (BIT C OF

STATUS REGISTER)

PKV RESET

LOW WHEN

RSTATUS

IS READ

READ

RSTATUS

VAP, VBP, OR VCP

Figure 17. Peak Detection

Bits 2 and 3 of the measurement mode register define the phase

supporting the peak detection. Current and voltage of this phase

can be monitored at the same time. Figure 17 shows a line

voltage exceeding a threshold set in the voltage peak register

(VPEAK[7:0]). The voltage peak event is recorded by setting

the PKV flag in the interrupt status register. If the PKV enable

bit is set to Logic 1 in the interrupt enable register, the

IRQ

logic output goes active low. See the Interrupts section.

Peak Level Set

The contents of the VPEAK and IPEAK registers compare to

the absolute value of the most significant byte output of the

selected voltage and current channels, respectively. Thus, for

example, the nominal maximum code from the current channel

ADC with a full-scale signal is 28F5C2h. See the Current

Channel Sampling section. Therefore, writing 28h to the

IPEAK register will put the current channel peak detection level

at full scale and set the current peak detection to its least sensi-

tive value. Writing 00h puts the current channel detection level at

zero. The detection is done when the content of the IPEAK

TEMPERATURE MEASUREMENT

The ADE7754 also includes an on-chip temperature sensor. A

temperature measurement is made every 4/CLKIN seconds.

The output from the temperature sensing circuit is connected

to an ADC for digitizing. The resulting code is processed and

placed into the temperature register (TEMP[7:0]) which can

be read by the user and has an address of 08h. See the Serial

Interface section. The contents of the temperature register are

signed (twos complement) with a resolution of 4

°C/LSB. The

temperature register produces a code of 00h when the ambient

temperature is approximately 129

°C. The value of the register is

temperature register = (temperature (

°C) – 129)/4. The tempera-

ture in the ADE7754 has an offset tolerance of approximately

±5°C. The error can be easily calibrated out by an MCU.

PHASE COMPENSATION

When the HPFs are disabled, the phase difference between the

current channel (IA, IB, and IC) and the voltage channel (VA,

VB, and VC) is zero from dc to 3.3 kHz. When the HPFs are

enabled, the current channels have a phase response as shown in

Figure 18a and 18b. The magnitude response of the filter is

shown in Figure 18c. As seen from in the plots, the phase response

is almost zero from 45 Hz to 1 kHz. This is all that is required

in typical energy measurement applications.

FREQUENCY (Hz)

0.07

0.05

0.03

0.01

–0.01

200

400

600

800

0.06

0.04

0.02

100

300

500

700

900

Figure 18a. Phase Response of the HPF and

Phase Compensation (10 Hz to 1 kHz)

FREQUENCY (Hz)

0.008

0.004

–0.004

0.010

0.006

0.002

–0.002

Figure 18b. Phase Response of the HPF and

Phase Compensation (40 Hz to 70 Hz)

FREQUENCY (Hz)

0.008

0.004

–0.004

0.010

0.006

0.002

–0.002

Figure 18c. Gain Response of HPF and Phase Com-

pensation (Deviation of Gain as % of Gain at 54 Hz)

Despite being internally phase compensated, the ADE7754 must

work with transducers that may have inherent phase errors. For

example, a phase error of 0.1

° to 0.3° is not uncommon for a CT

(current transformer). These phase errors can vary from part to

part, and they must be corrected in order to perform accurate

power calculations. The errors associated with phase mismatch

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