ADE7754_15 datasheet(13/44 Pages) AD

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ADE7754

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In addition to the enable bits, the zero-crossing detection interrupt

of each phase is enabled/disabled by setting the ZXSEL bits of the

MMODE register (Address 0Bh) to Logic 1 or 0, respectively.

Zero-Crossing Timeout

Each zero-crossing detection has an associated internal timeout

ter is decremented (1 LSB) every 384/CLKIN seconds. The

registers are reset to a common user programmed value (i.e.,

zero cross timeout register—ZXTOUT, Address 12h) every

time a zero crossing is detected on its associated input. The

default value of ZXTOUT is FFFFh. If the internal register

decrements to zero before a zero crossing at the corresponding

input is detected, it indicates an absence of a zero crossing in

the time determined by the ZXTOUT. The ZXTO detection

bit of the corresponding phase in the interrupt status register is

then switched on (Bits 4 to 6). An active low on the

IRQ output

also appears if the SAG enable bit for the corresponding phase

in the interrupt enable register is set to Logic 1.

In addition to the enable bits, the zero-crossing timeout detec-

tion interrupt of each phase is enabled/disabled by setting the

ZXSEL bits of the MMODE register (Address 0Bh) to Logic 1

or Logic 0, respectively. When the zero-crossing timeout detection

is disabled by this method, the ZXTO flag of the corresponding

phase is switched on all the time.

Figure 15 shows the mechanism of the zero-crossing timeout

detection when the line voltage A stays at a fixed dc level for

more than CLKIN/384

ZXTOUT seconds.

VOLTAGE

CHANNEL A

ZXTOA

DETECTION BIT

16-BIT INTERNAL

ZXTOUT

Figure 15. Zero-Crossing Timeout Detection

PERIOD MEASUREMENT

The ADE7754 also provides the period measurement of the

line voltage. The period is measured on the phase specified by

Bits 0 to 1 of the MMODE register. The period register is an

unsigned 15-bit register and is updated every period of the

selected phase. Bits 0 and 1 and Bits 4 to 6 of the MMODE

selections should indicate the same phase. The ZXSEL bits of

the MMODE register (Bits 4 to 6) enable the phases on which

the period measurement can be done. The PERDSEL bits

select the phase for period measurement within the phases

selected by the ZXSEL bits.

The resolution of this register is 2.4

µs/LSB when CLKIN =

10 MHz, which is 0.014% when the line frequency is 60 Hz.

When the line frequency is 60 Hz, the value of the period regis-

ter is approximately 6944d. The length of the register enables

the measurement of line frequencies as low as 12.7 Hz.

LINE VOLTAGE SAG DETECTION

The ADE7754 can be programmed to detect when the absolute

value of the line voltage of any phase drops below a certain peak

value for a number of half cycles. All phases of the voltage chan-

nel are controlled simultaneously. This condition is illustrated

in Figure 16.

SAGCYC[7:0] = 06h

6 HALF CYCLES

SAGLVL[7:0]

FULL SCALE

SAG INTERRUPT

FLAG (BIT 1 TO

BIT 3 OF STATUS

SAG EVENT RESET

LOW WHEN VOLTAGE

CHANNEL EXCEEDS

SAGLVL[7:0]

READ

RSTATUS

VAP, VBP, OR VCP

Figure 16. SAG Detection

Figure 16 shows a line voltage falling below a threshold set in

the SAG level register (SAGLVL[7:0]) for nine half cycles.

Since the SAG cycle register indicates a six half-cycle thresh-

old (SAGCYC[7:0]=06h), the SAG event is recorded at the

end of the sixth half-cycle by setting the SAG flag of the corre-

sponding phase in the interrupt status register (Bits 1 to 3 in the

interrupt status register). If the SAG enable bit is set to Logic 1

for this phase (Bits 1 to 3 in the interrupt enable register), the

IRQ logic output goes active low. See the Interrupts section. All

the phases are compared to the same parameters defined in the

SAGLVL and SAGCYC registers.

SAG Level Set

The content of the SAG level register (one byte) is compared to

the absolute value of the most significant byte output from the

voltage channel ADC. Thus, for example, the nominal maximum

code from the voltage channel ADC with a full-scale signal is

28F5h. See the Voltage Channel ADC section.

Therefore, writing 28h to the SAG level register puts the SAG

detection level at full scale and sets the SAG detection to its

most sensitive value.

Writing 00h puts the SAG detection level at 0. The detection of

a decrease of an input voltage is in this case hardly possible.

The detection is made when the content of the SAGLVL

PEAK DETECTION

The ADE7754 also can be programmed to detect when the

absolute value of the voltage or the current channel of one phase

exceeds a certain peak value. Figure 17 illustrates the behavior

of the peak detection for the voltage channel.

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