ADE7754_15 datasheet(27/44 Pages) AD

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REV. 0

ADE7754

–27–

The number of half line cycles is specified in the LINCYC unsigned

16-bit register. The ADE7754 can accumulate apparent power

for up to 65535 combined half cycles. Because the apparent

power is integrated on the same integral number of line cycles as

the line active energy register, these two values can be compared

easily. See the Energies Scaling section. The active and apparent

energy are calculated more accurately because of this precise

timing control and provide all the information needed for reactive

power and power factor calculation. At the end of an energy

calibration cycle, the LINCYC flag in the interrupt status register

is set. If the LINCYC enable bit in the interrupt enable register

is set to Logic 1, the

IRQ output also goes active low. Thus the

IRQ line can also be used to signal the end of a calibration.

The total apparent power calculated by the ADE7754 in the

line accumulation mode depends on the configuration of the

VAMOD bits in the VAMode register. Each term of the formula

used can be disabled or enabled by the LVASEL bits of the

VAMode register. The different configurations are described in

Table VI.

Table VI. Total Line Apparent Energy Calculation

VAMOD VASEL0

VASEL1

VASEL2

VARMS

× I

ARMS

+ VBRMS

× I

BRMS

+ VCRMS

× I

CRMS

VARMS

× I

ARMS

+(VARMS + VCRMS)

× I

BRMS

+ VCRMS

× I

CRMS

VARMS

× I

ARMS

+ VARMS

× I

BRMS

+ VCRMS

× I

CRMS

The line apparent energy accumulation uses the same signal

path as the apparent energy accumulation. The LSB size of

these two registers is equivalent.

The ADE7754 accumulates the total reactive power signal in

the LAENERGY register. This mode is selected by setting to

Logic 1 Bit 5 of the WAVMode register (Address 0Ch). When

this bit is set, the accumulation of the active energy over half

line cycles in the LAENERGY register is disabled and done

instead in the LVAENERGY register. In this mode, the accu-

LVAENERGY[23:0]

VADIV

APPARENT

POWER

PHASE B

APPARENT

POWER

PHASE A

APPARENT

POWER

PHASE C

LPF1

FROM VA

ADC

ZERO-CROSS

DETECT

MMODE

LPF1

FROM VB

ADC

ZERO-CROSS

DETECT

MMODE

LPF1

FROM VC

ADC

ZERO-CROSS

DETECT

MMODE

CALIBRATION

CONTROL

LINCYC[15:0]

ACCUMULATE APPARENT POWER

DURING LINCYC ZERO CROSSINGS

Figure 39. Apparent Energy Calibration

mulation of the apparent energy over half line cycles in the

LVAENERGY is no longer available. See Figure 33. Since the

LVAENERGY register is an unsigned value, the accumulation

of the active energy in the LVAENERGY register is unsigned.

In this mode (reactive energy), the selection of the phases

accumulated in the LAENERGY and LVAENERGY registers

is done by the LWATSEL selection bits of the WATMode

ENERGIES SCALING

The ADE7754 provides measurements of the active, reactive,

and apparent energies. These measurements do not have the

same scaling and thus cannot be compared directly to each other.

Energy

Type

PF = 1

PF = 0.707

PF = 0

ActiveWh

0.707

Reactive0

0.707 / 9.546

Wh / 9.546

ApparentWh / 3.657

Wh / 3.657

CHECK SUM REGISTER

The ADE7754 has a checksum register (CHECKSUM[5:0]) to

ensure that the data bits received in the last serial read operation

are not corrupted. The 6-bit checksum register is reset before

the first bit (MSB of the register to be read) is put on the

DOUT pin. During a serial read operation, when each data bit

becomes available on the rising edge of SCLK, the bit is added

to the checksum register. In the end of the serial read operation,

the content of the checksum register will equal the sum of all

ones in the register previously read. Using the checksum regis-

ter, the user can determine whether an error has occurred during

the last read operation. Note that a read to the checksum register

also generates a checksum of the checksum register itself.

CONTENT OF REGISTER (n-BYTES)

DOUT

CHECKSUM

ADDR: 3Eh

Figure 40. Checksum Register for Serial Interface Read

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