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ADE7754

APPARENT ENERGY CALCULATION

The apparent energy is given as the integral of the apparent

power.

Apparent Energy

Apparent Power t dt

= ∫

()

(21)

The ADE7754 achieves the integration of the apparent power

signal by continuously accumulating the apparent power signal

in an internal nonreadable 49-bit register. The apparent energy

this internal register. This discrete time accumulation or summa-

tion is equivalent to integration in continuous time. Equation 22

expresses the relationship, where n is the discrete time sample

number and T is the sample period.

Apparent Energy

Lim

Apparent Power nT

=×

















→

∞

∑

()

(22)

The discrete time sample period (T) for the accumulation regis-

ter in the ADE7754 is 1.2

µs (12/10 MHz).

Figure 37 shows a graphical representation of this discrete

time integration or accumulation. The apparent power signal

is continuously added to the internal register. This addition is

a signed addition even if the apparent energy theoretically

always remains positive.

VAENERGY[23:0]

VADIV

TOTAL APPARENT POWER IS

ACCUMULATED (INTEGRATED) IN

THE APPARENT ENERGY REGISTER

TOTAL APPARENT POWER

00000h

D1B71h

TIME (nT)

APPARENT POWER

SIGNAL – P

Figure 37. Apparent Energy Calculation

The upper 49-bit value of the internal register is divided by

VADIV. If the value in the VADIV register is 0, then the internal

active energy register is divided by 1. VADIV is an 8-bit unsigned

apparent energy register (VAENERGY[23:0]). RVAENERGY

Figure 38 shows this apparent energy accumulation for full-scale

(sinusoidal) signals on the analog inputs. The three curves illus-

trate the minimum time it takes the energy register to roll over

when the individual VA gain registers contents all equal 3FFh,

000h, and 800h. The VA gain registers are used to carry out an

apparent power calibration in the ADE7754. The fastest integra-

tion time occurs when the VA gain registers are set to maximum

full scale (i.e., 3FFh).

00,0000h

7F,FFFFh

80,0000h

3F,FFFFh

40,0000h

VAENERGY[23:0]

TIME (sec)

AVAG = BVAG = CVAG = 3FFh

131

262

393

65.5

AVAG = BVAG = CVAG = 000h

AVAG = BVAG = CVAG = 800h

196.5

327.5

Figure 38. Energy Register Roll Over Time for Full-

Scale Power (Minimum and Maximum Power Gain)

Note that the apparent energy register contents roll over to full-

scale negative (80,0000h) and continue increasing in value when

the power or energy flow is positive, as shown in Figure 38. By

using the interrupt enable register, the ADE7754 can be config-

ured to issue an interrupt

(IRQ) when the apparent energy

Integration Times under Steady Load

As described in the preceding section, the discrete time sample

period (T) for the accumulation register is 1.2

µs (12/CLKIN).

With full-scale sinusoidal signals on the analog inputs and the

VA gain registers set to 000h, the average word value from each

apparent power stage is D1B71h. See the Apparent Power

Calculation section. The maximum value that can be stored in

the apparent energy register before it overflows is 22

3 – 1 or

FF,FFFFh. As the average word value is added to the internal

overflows, the integration time under these conditions with

VADIV = 0 is calculated as follows:

Time

FFFF FFFF FFFFh

×=

min

31 71

131

When VADIV is set to a value different from 0, the integration

time varies as shown in Equation 23.

Time

VADIV

WDIV

=×

(23)

LINE APPARENT ENERGY ACCUMULATION

The ADE7754 is designed with a special apparent energy accu-

mulation mode that simplifies the calibration process. By using

the on-chip zero-crossing detection, the ADE7754 accumulates

the apparent power signal in the LVAENERGY register for an

integral number of half cycles, as shown in Figure 39. The line

apparent energy accumulation mode is always active.

Each of three zero-crossing detection phases can contribute to

the accumulation of the half line cycles. Phase A, B, and C zero

crossings are taken into account when counting the number of

half line cycles by setting Bits 4 to 6 of the MMODE register to

Logic 1. Selecting phases for the zero-crossing counting also has

the effect of enabling the zero-crossing detection, zero-crossing

timeout, and period measurement for the corresponding phase

as described in the zero-crossing detection paragraph.

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