ADE7754_15 datasheet(4/44 Pages) AD

4 / 44 page

REV. 0

–4–

ADE7754

TIMING CHARACTERISTICS1, 2

(AVDD = DVDD = 5 V

5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 10 MHz XTAL,

TMIN to TMAX = –40 C to +85 C, unless otherwise noted.)

Parameter

Spec

Unit

Test Conditions/Comments

Write Timing

ns (min)

CS Falling Edge to First SCLK Falling Edge

ns (min)

SCLK Logic High Pulsewidth

ns (min)

SCLK Logic Low Pulsewidth

ns (min)

Valid Data Setup Time before Falling Edge of SCLK

ns (min)

Data Hold Time after SCLK Falling Edge

400

ns (min)

Minimum Time between the End of Data Byte Transfers

ns (min)

Minimum Time between Byte Transfers during a Serial Write

100

ns (min)

CS Hold Time after SCLK Falling Edge

Read Timing

µs (min)

Minimum Time between Read Command (i.e., a Write to Communication

t10

ns (min)

Minimum Time between Data Byte Transfers during a Multibyte Read

t11

ns (min)

Data Access Time after SCLK Rising Edge following a Write to the

Communications Register

t12

100

ns (max)

Bus Relinquish Time after Falling Edge of SCLK

ns (min)

t13

100

ns (max)

Bus Relinquish Time after Rising Edge of

ns (min)

NOTES

1Sample tested during initial release and after any redesign or process change

that may affect this parameter. All input signals are specified with tr = tf = 5 ns

(10% to 90%) and timed from a voltage level of 1.6 V.

2See timing diagrams below and Serial Interface section of this data sheet.

3Minimum time between read command and data read for all registers except

wavmode register, which is t9 = 500 ns min.

4Measured with the load circuit in Figure 1 and defined as the time required for

the output to cross 0.8 V or 2.4 V.

5Derived from the measured time taken by the data outputs to change 0.5 V

when loaded with the circuit in Figure 1. The measured number is then

extrapolated back to remove the effects of charging or discharging the 50 pF

capacitor. The time quoted in the timing characteristics is the true bus relin-

quish time of the part and is independent of the bus loading.

OUTPUT

50pF

1.6mA

200 A

IOH

IOL

2.1V

Figure 1. Load Circuit for Timing Specifications

SCLK

DIN

DB7

MOST SIGNIFICANT BYTE

t2 t3

DB0

DB7

DB0

LEAST SIGNIFICANT BYTE

COMMAND BYTE

Figure 2. Serial Write Timing

SCLK

DIN

t11

t12

DB7

DOUT

t13

DB0

DB7

t10

MOST SIGNIFICANT BYTE

LEAST SIGNIFICANT BYTE

COMMAND BYTE

Figure 3. Serial Read Timing

ADE7754 датащи(PDF) 4 Page - Analog Devices

ADE7754 датащи(HTML) 4 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

датащи скачать

ссылки URL