PRIXP425BD datasheet(111/112 Pages) INTEL

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Intel® IXP42X Product Line and IXC1100 Control Plane Processor

Electrical Specifications

Datasheet

111

NOTES:

1. TRELEASE_PWRON_RST_N is the time required for the internal oscillator to reach stability. When an external

oscillator is being used in place of a crystal, the 500-ms delay is not required.

2. The expansion bus address is captured as a derivative of the RESET_IN_N signal going high. When a

programmable-logic device is used to drive the EX_ADDR signals instead of pull-downs, the signals must be

active until PLL_LOCK is active.

3. PLL_LOCK is deasserted immediately when watchdog timer event occurs, or when RESET_IN_N is

asserted, or when PWRON_RST_N is asserted. PLL_LOCK remains deasserted for ~24 ref_clocks after the

watchdog reset is deasserted (internal to the chip). A ref clock time period is 1/CLKIN.

5.6

Power Sequence

The 3.3-V I/O voltage (VCCP) must be powered up 1 µs before the core voltage (VCC). The

IXP42X product line and IXC1100 control plane processors’ core voltage (VCC) must never

become stable prior to the 3.3-V I/O voltage (VCCP). The VCCOSC, VCCPLL1, and VCCPLL2

voltages follow the VCC power-up pattern. The VCCOSCP follows the VCCP power-up pattern. The

value for TPOWER_UP must be at least 1 µs. The TPOWER_UP timing parameter is measured from

VCCP at 3.3 V and VCC at 1.3 V. There are no power-down requirements for the IXP42X product

line and IXC1100 control plane processors.

Table 65.

Reset Timings Table Parameters

Symbol

Parameter

Min.

Typ.

Max.

Units

Note

TRELEASE_PWRON_RST_N

Minimum time required to hold the

PWRON_RST_N at logic 0 state after

stable power has been applied to the

IXP42X product line and IXC1100 control

plane processors. When using a crystal

to drive the processors’ system clock.

(OSC_IN and OSC_OUT)

500

TRELEASE_RESET_IN_N

Minimum time required to hold the

RESET_IN_N at logic 0 state after

PWRON_RST_N has been released to a

logic 1 state. The RESET_IN_N signal

must be held low when the

PWRON_RST_N signal is held low.

TPLL_LOCK

Maximum time for PLL_LOCK signal to

drive to logic 1 after RESET_IN_N is

driven to logic 1 state. The boot

sequence does not occur until this period

is complete.

µs

TEX_ADDR_SETUP

Minimum time for the EX_ADDR signals

to drive the inputs prior to RESET_IN_N

being driven to logic 1 state. This is used

for sampling configuration information.

TEX_ADDR_HOLD

Minimum/maximum time for the

EX_ADDR signals to drive the inputs

prior to PLL_LOCK being driven to logic 1

state. This is used for sampling

configuration information.

020

TWARM_RESET

Minimum time required to drive

RESET_IN_N signal to logic 0 in order to

cause a reset after the IXP42X product

line and IXC1100 control plane

processors has been in normal operation.

The power must remain stable and the

PWRON_RST_N signal must remain

stable.

500

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