PRIXP425BD datasheet(23/112 Pages) INTEL

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Intel® IXP42X Product Line and IXC1100 Control Plane Processor

Functional Overview

Datasheet

2.1.14

Timers

The IXP42X product line and IXC1100 control plane processors consists of four internal timers

operating at 66.66 MHz (which is 2 * OSC_IN input pin.) to allow task scheduling and prevent

software lock-ups. The device has four 32-bit counters:

2.1.15

AHB Queue Manager

The AHB Queue Manager (AQM) provides queue functionality for various internal blocks. It

maintains the queues as circular buffers in an embedded 8KB SRAM. It also implements the status

flags and pointers required for each queue.

The AQM manages 64 independent queues. Each queue is configurable for buffer and entry size.

Additionally status flags are maintained for each queue.

The AQM interfaces include an Advanced High-performance Bus (AHB) interface to the NPEs

and Intel XScale core (or any other AHB bus master), a Flag Bus interface, an event bus (to the

NPE condition select logic) and two interrupts to the Intel XScale core. The AHB interface is used

for configuration of the AQM and provides access to queues, queue status and SRAM. Individual

queue status for queues 0-31 is communicated to the NPEs via the flag bus. Combined queue status

for queues 32-63 are communicated to the NPEs via the event bus. The two interrupts, one for

queues 0-31 and one for queues 32-63, provide status interrupts to the Intel XScale core.

2.2

Intel XScale® Core

The Intel XScale® Core technology is compliant with the ARM* Version 5TE instruction-set

architecture (ISA). The Intel XScale core — shown in Figure 5 — is designed with Intel

state-of-the-art, 0.18-µ-production semiconductor process technology. This process technology

enables the Intel XScale core to operate over a wide speed and power range, producing

industry-leading mW/MIPS performance.

Intel XScale core features include:

• Seven/eight-stage super-pipeline promotes high-speed, efficient core performance

• 128-entry branch target buffer keeps pipeline filled with statistically correct branch choices

• 32-entry instruction memory-management unit for logical-to-physical address translation,

access permissions, I-cache attributes

• 32-entry data-memory management unit for logical-to-physical address translation, access

permissions, D-cache attributes

• 32-Kbyte instruction cache can hold entire programs, preventing core stalls caused by

multi-cycle memory accesses

• 32-Kbyte data cache reduces core stalls caused by multi-cycle memory accesses

• 2-Kbyte mini-data cache for frequently changing data streams avoids “thrashing” of the

D-cache

• Four-entry fill-and-pend buffers to promote core efficiency by allowing “hit-under-miss”

operation with data caches

• Watch-Dog Timer

• Timestamp Timer

• Two general-purpose timers

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