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PRIXP425BD датащи(PDF) 98 Page - Intel Corporation

номер детали PRIXP425BD
подробное описание детали  Intel짰 IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
PDF  112 Pages
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производитель  INTEL [Intel Corporation]
домашняя страница  http://www.intel.com
Logo INTEL - Intel Corporation

PRIXP425BD датащи(HTML) 98 Page - Intel Corporation

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Intel® IXP42X Product Line and IXC1100 Control Plane Processor
Electrical Specifications
98
Datasheet
NOTES:
1. EX_ALE is not valid in simplex mode of operation.
2. Setting the address phase parameter (T1) will adjust the duration that the address appears to the external device.
3. Setting the data setup phase parameter (T2) will adjust the duration that the data appears prior to a data
strobe (read or write) to an external device.
4. Setting the data strobe phase parameter (T3) will adjust the duration that the data strobe appears (read or
write) to an external device. Data will be available during this time as well.
5. Setting the data hold strobe phase parameter (T4) will adjust the duration that the chip selects, address, and
data (during a write) will be held.
6. Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on the
expansion interface.
7. One cycle is the period of the Expansion Bus clock.
8. Clock to output delay for all signals will be a maximum of 15 ns for devices requiring operation in
synchronous mode.
9. Timing tests were performed with a 70-pF capacitor to ground.
Table 55.
Motorola* Simplex Mode Values
Symbol
Parameter
Min.
Max.
Units
Note
s
Tad2valcs
Valid address to valid chip select
1
4
Cycles
1, 2,
7
Tdval2valds
Write data valid prior to EXP_MOT_DS_N falling edge
1
4
Cycles
3, 7
Tdspulse
Pulse width of the EXP_MOT_DS_N
1
16
Cycles
4, 7
Tdholdafterds
Valid data after the rising edge of EXP_MOT_DS_N
1
4
Cycles
5, 7
Trdsetup
Data valid required before the rising edge of
EXP_MOT_DS_N
5.3
14.7
ns
Trdhold
Data hold required after the rising edge of
EXP_MOT_DS_N
2ns
Trecov
Time required between successive accesses on the
expansion interface.
116
Cycles
6



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