PRIXP425BD datasheet(96/112 Pages) INTEL

96 / 112 page

Intel® IXP42X Product Line and IXC1100 Control Plane Processor

Electrical Specifications

Datasheet

NOTES:

1. The EX_ALE signal is extended form 1 to 4 cycles based on the programming of the T1 timing parameter.

The parameter Tale2addrhold is fixed at 1 cycle

2. Setting the address phase parameter (T1) will adjust the duration that the address appears to the external device.

3. Setting the data setup phase parameter (T2) will adjust the duration that the data appears prior to a data

strobe (read or write) to an external device.

4. Setting the data strobe phase parameter (T3) will adjust the duration that the data strobe appears (read or

write) to an external device. Data will be available during this time as well.

5. Setting the data hold strobe phase parameter (T4) will adjust the duration that the chip selects, address, and

data (during a write) will be held.

6. Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on the

expansion interface.

7. One cycle is the period of the Expansion Bus clock.

8. Clock to output delay for all signals will be a maximum of 15 ns for devices requiring operation in

synchronous mode.

9. Timing tests were performed with a 70-pF capacitor to ground.

Table 54.

Motorola* Multiplexed Mode Values

Symbol

Parameter

Min.

Max.

Units

Notes

Talepulse

Pulse width of ALE (ADDR is valid at the rising edge of ALE)

Cycles 1, 7

Tale2addrhold Valid address hold time after from falling edge of ALE

Cycles 1, 2, 7

Tdval2valds

Write data valid prior to EXP_MOT_DS_N falling edge

Cycles 3, 7

Tdspulse

Pulse width of the EXP_MOT_DS_N

Cycles 4, 7

Tdholdafterds Valid data after the rising edge of EXP_MOT_DS_N

Cycles 5, 7

Tale2valcs

Valid chip select after the falling edge of ALE

Cycles 7

Trdsetup

Data valid required before the rising edge of EXP_MOT_DS_N

5.3

14.7

Trdhold

Data hold required after the rising edge of EXP_MOT_DS_N

Trecov

Time needed between successive accesses on expansion

interface.

116

Cycles 6

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