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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PRIXP425BD датащи(PDF) 89 Page - Intel Corporation |
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PRIXP425BD датащи(HTML) 89 Page - Intel Corporation |
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89 / 112 page  Intel® IXP42X Product Line and IXC1100 Control Plane Processor Electrical Specifications Datasheet 89 5.5.2.3 UTOPIA-2 NOTES: 1. Timing was tested with a 70-pF capacitor to ground. Figure 17. UTOPIA-2 Input Timings Table 45. UTOPIA-2 Input Timings Values Symbol Parameter Min. Max. Units Notes Tsetup Input setup prior to rising edge of clock. Inputs included in this timing are UTP_IP_DATA[7:0], UTP_IP_SOC, AND UTP_IP_FCI, and UTP_OP_FCI. 8ns Thold Input hold time after the rising edge of the clock. Inputs included in this timing are UTP_IP_DATA[7:0], UTP_IP_SOC, and UTP_IP_FCI, and UTP_OP_FCI. 1ns Figure 18. UTOPIA-2 Output Timings Table 46. UTOPIA-2 Output Timings Values Symbol Parameter Min. Max. Units Notes Tclk2out Rising edge of clock to signal output. Outputs included in this timing are UTP_IP_DATA[3:0], UTP_OP_SOC, UTP_OP_FCO, UTP_IP_FCO, UTP_OP_DATA[7:0], and UTP_OP_ADDR[3:0]. 17 ns 1 Tholdout Signal output hold time after the rising edge of the clock. Outputs included in this timing are UTP_IP_DATA[3:0], UTP_OP_SOC, UTP_OP_FCO, UTP_IP_FCO, UTP_OP_DATA[7:0], and UTP_OP_ADDR[3:0]. 1ns 1 A9578-01 Thold Tsetup Clock Signals A9579-01 Tclk2out Tholdout Clock Signals |
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