PRIXP425BD datasheet(31/112 Pages) INTEL

31 / 112 page

Intel® IXP42X Product Line and IXC1100 Control Plane Processor

Functional Signal Descriptions

Datasheet

This section’s other tables include:

• Table 5 — SDRAM Interface signals

• Table 6 — PCI Controller signals

• Table 7 — High-Speed, Serial Interface 0 signals

• Table 8 — High-Speed, Serial Interface 1 signals

• Table 9 — MII Interfaces signals

• Table 10 — UTOPIA-2 Interface signals

• Table 11 — Expansion Bus Interface signals

• Table 12 — UART Interfaces signals

• Table 13 — USB Interface signals

• Table 14 — Oscillator Interface signals

• Table 15 — GPIO Interface signals

• Table 16 — JTAG Interface signals

• Table 17 — System Interface signals

• Table 18 — Power Interface signals

Note:

1. The Power On Reset Column of the Tables indicate the state of the signals during the Power On Reset

process

2. The Reset Column of the Tables indicate the state of the signals during the Reset.

Table 5.

SDRAM Interface (Sheet 1 of 2)

Name

Power

Reset†

Reset† Type†

Description

SDM_ADDR[12:0]

SDRAM Address: A0-A12 signals are output during the READ/WRITE

commands and ACTIVE commands to select a location in memory to act

upon.

SDM_DATA[31:0]

1I/O

SDRAM Data: Bidirectional data bus used to transfer data to and from the

SDRAM

SDM_CLKOUT

SDRAM Clock: All SDRAM input signals are sampled on the rising edge

of SDM_CLKOUT. All output signals are driven with respect to the rising

edge of SDM_CLKOUT.

SDM_BA[1:0]

SDRAM Bank Address: SDM_BA0 and SDM_BA1 define the bank the

current command is attempting to access.

SDM_RAS_N

SDRAM Row Address strobe/select (active low): Along with

SDM_CAS_N, SDM_WE_N, and SDM_CS_N signals determines the

current command to be executed.

SDM_CAS_N

SDRAM Column Address strobe/select (active low): Along with

SDM_RAS_N, SDM_WE_N, and SDM_CS_N signals determines the

current command to be executed.

SDM_CS_N[1:0]

SDRAM Chip select (active low): CS# enables the command decoder in

the external SDRAM when logic low and disables the command decoder

in the external SDRAM when logic high.

SDM_WE_N

SDRAM Write enable (active low): Along with SDM_CAS_N,

SDM_RAS_N, and SDM_CS_N signals determines the current command

to be executed.

† For a legend of the

Type codes, see Table 4 on page 30.

PRIXP425BD датащи(PDF) 31 Page - Intel Corporation

PRIXP425BD датащи(HTML) 31 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL