PRIXP425BD datasheet(34/112 Pages) INTEL

34 / 112 page

Intel® IXP42X Product Line and IXC1100 Control Plane Processor

Functional Signal Descriptions

Datasheet

PCI_GNT_N[0]

I/O

PCI arbitration grant:

•

When configured as an output (PCI arbiter enabled), the internal PCI

arbiter to allow an agent to claim control of the PCI bus.

•

When configured as an input (PCI arbiter disabled), the pin will be

used to claim access of the PCI bus from an external arbiter.

Should be pulled high with a 10-K

Ω resistor when not being utilized in the

system.

PCI_INTA_N

O/D

PCI interrupt: Used to request an interrupt.

Should be pulled high with a 10-K

Ω resistor when not being utilized in the

system.

PCI_CLKIN

PCI Clock: provides timing for all transactions on PCI. All PCI signals —

except INTA#, INTB#, INTC#, and INTD# — are sampled on the rising edge of

CLK and timing parameters are defined with respect to this edge. The PCI

clock rate can operate at up to 66 MHz.

Should be pulled low with a 10-K

Ω resistor when not being utilized in the

system.

Table 7.

High-Speed, Serial Interface 0

Name

Power

Reset†

Reset† Type†

Description

HSS_TXFRAME0

I/O

The High-Speed Serial (HSS) transmit frame signal can be configured as

an input or an output to allow an external source become synchronized

with the transmitted data. Often known as a Frame Sync signal.

Configured as an input upon reset.

Should be pulled low with a 10-K

Ω resistor when not being utilized in the

system.

HSS_TXDATA0

O/D

Transmit data out. Open Drain output.

Must be pulled high with a 10-K

Ω resistor to VCCP.

HSS_TXCLK0

I/O

The High-Speed Serial (HSS) transmit clock signal can be configured as an

input or an output. The clock can be a frequency ranging from 512 KHz to

8.192 MHz. Used to clock out the transmitted data. Configured as an input

upon reset. Frame sync and data can be selected to be generated on the

rising or falling edge of the transmit clock.

Should be pulled low with a 10-K

Ω resistor when not being utilized in the

system.

HSS_RXFRAME0

I/O

The High-Speed Serial (HSS) receive frame signal can be configured as

an input or an output to allow an external source to become

synchronized with the received data. Often known as a Frame Sync

signal. Configured as an input upon reset.

Should be pulled low with a 10-K

Ω resistor when not being utilized in the

system.

HSS_RXDATA0

Receive data input. Can be sampled on the rising or falling edge of the

receive clock.

Should be pulled low through a 10-K

Ω resistor when not being utilized in

the system.

HSS_RXCLK0

I/O

The High-Speed Serial (HSS) receive clock signal can be configured as

an input or an output. The clock can be from 512 KHz to 8.192 MHz.

Used to sample the received data. Configured as an input upon reset.

Should be pulled low with a 10-K

Ω resistor when not being utilized in the

system.

Table 6.

PCI Controller (Sheet 2 of 2)

Name

Power

Reset†

Reset† Type†

Description

†

For a legend of the Type codes, see Table 4 on page 30.

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