PRIXP425BD datasheet(108/112 Pages) INTEL

108 / 112 page

Intel® IXP42X Product Line and IXC1100 Control Plane Processor

Electrical Specifications

108

Datasheet

NOTES:

1. HSS_TXCLK and HSS_RXCLK may be coming from external independent sources or being driven by the

IXP42X product line and IXC1100 control plane processors. The signals are shown to be synchronous for

illustrative purposes and are not required to be synchronous.

2. Applicable when the HSS_RXFRAME and HSS_TXFRAME signals are being driven by an external source

as inputs into the IXP42X product line and IXC1100 control plane processors. Always applicable to

HSS_RXDATA.

3. The HSS_RXFRAME and HSS_TXFRAME can be configured to accept data on the rising or falling edge of

the given reference clock. HSS_RXFRAME and HSS_RXDATA signals are synchronous to HSS_RXCLK

and HSS_TXFRAME and HSS_TXDATA signals are synchronous to the HSS_TXCLK.

4. Applicable when the HSS_RXFRAME and HSS_TXFRAME signals are being driven by the IXP42X product

line and IXC1100 control plane processors to an external source. Always applicable to HSS_TXDATA.

5. The HSS_TXCLK can be configured to be driven by an external source or be driven by the IXP42X product

line and IXC1100 control plane processors. The slowest clock speed that can be accepted or driven is

512 KHz. The maximum clock speed that can be accepted or driven is 8.192 MHz. The clock duty cycle

accepted will be 50/50 + 20%.

6. Timing tests were performed with a 70-pF capacitor to ground and a 10-KΩ pull-up resistor.

For more information on the HSS Jitter Specifications see the Intel® IXP42X Product Line of

Network Processors and IXC1100 Control Plane Processor Developer’s Manual

Table 63.

High-Speed, Serial Timing Values

Symbol

Parameter

Min.

Max.

Units

Notes

Setup time of HSS_TXFRAME, HSS_RXFRAME, and

HSS_RXDATA prior to the rising edge of clock

5ns

1, 2, 3

Hold time of HSS_TXFRAME, HSS_RXFRAME, and

HSS_RXDATA after the rising edge of clock

0ns

1, 2, 3

Setup time of HSS_TXFRAME, HSS_RXFRAME, and

HSS_RXDATA prior to the falling edge of clock

5ns

1, 2, 3

Hold time of HSS_TXFRAME, HSS_RXFRAME, and

HSS_RXDATA after the falling edge of clock

0ns

1, 2, 3

Rising edge of clock to output delay for

HSS_TXFRAME, HSS_RXFRAME, and HSS_TXDATA

1, 4

Falling edge of clock to output delay for

HSS_TXFRAME, HSS_RXFRAME, and HSS_TXDATA

1, 3, 4

Output Hold Delay after rising edge of final clock for

HSS_TXFRAME, HSS_RXFRAME, and HSS_TXDATA

0ns

1, 3, 4

Output Hold Delay after falling edge of final clock for

HSS_TXFRAME, HSS_RXFRAME, and HSS_TXDATA

0ns

1,3, 4

HSS_TXCLK period and HSS_RXCLK period

1/8.192 MHz 1/512 KHz

PRIXP425BD датащи(PDF) 108 Page - Intel Corporation

PRIXP425BD датащи(HTML) 108 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL