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PRIXP425BD датащи(PDF) 93 Page - Intel Corporation |
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PRIXP425BD датащи(HTML) 93 Page - Intel Corporation |
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93 / 112 page ![]() Intel® IXP42X Product Line and IXC1100 Control Plane Processor Electrical Specifications Datasheet 93 NOTES: 1. Timing test were performed with a 70-pF load to ground. 5.5.2.7 Expansion Bus Figure 24. SDRAM Output Timings Table 51. SDRAM Output Timings Values Symbol Parameter Min. Max. Units Notes Tclk2out Rising edge of clock-to-signal output. Outputs included in this timing are SDM_ADDR[12:0], SDM_BA[1:0], SDM_DQM[3:0], SDM_CKE, SDM_WE_N, SDM_CS_N[1:0], SDM_CAS_N, SDM_RAS_N, SDM_DQ[31:0] (during a write operation). 5.5 ns 1 Tholdout Signal output hold time after the rising edge of the clock. Outputs included in this timing are SDM_DQ[31:0] (during a write operation). 1.5 ns 1 A9584-01 Tclk2out Tholdout Data Valid Clock Signals Figure 25. Intel Multiplexed Mode A9585-01 EX_CLK EX_ADDR EX_DATA EX_RD_N EX_DATA EX_ALE EX_WR_N EX_CS_N Valid Address T5 1-16 Cycles T4 1-4 Cycles Trecov Tale2addrhold Trdsetup Trdhold Tdval2valwrt Tdhold2afterwr T3 1-16 Cycles T2 1-4 Cycles T1 2-5 Cycles ALE Extended Talepulse Tale2valcs Twrpulse Address Output Data Address Input Data Multiplexed Address/Data |
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