PRIXP425BD datasheet(88/112 Pages) INTEL

88 / 112 page

Intel® IXP42X Product Line and IXC1100 Control Plane Processor

Electrical Specifications

Datasheet

NOTES:

1. See the timing measurement conditions.

2. Parts compliant to the 3.3 V signaling environment.

3. REQ# and GNT# are point-to-point signals and have different output valid delay and input setup times than

do bused signals. GNT# has a setup of 10 ns for 33 MHz and 5 ns for 66 MHz; REQ# has a setup of 12 ns for

33 MHz and 5 ns for 66 MHz.

4. RST# is asserted and de-asserted asynchronously with respect to CLK.

5. All PCI outputs must be asynchronously driven to a tri-state value when RST# is active.

6. Setup time applies only when the device is not driving the pin. Devices cannot drive and receive signals at

the same time.

7. Timing was tested with a 70-pF capacitor to ground.

8. For additional information, see the PCI Local Bus Specification, Rev. 2.2.

5.5.2.2

USB Interface

For timing parameters, see the USB 1.1 specification. The IXP42X product line and IXC1100

control plane processors’ USB 1.1 interface is a device or function controller only. The IXP42X

product line and IXC1100 control plane processors’ USB v 1.1 interface cannot be line-powered.

Table 44.

PCI Bus Signal Timings

Symbol

Parameter

33 MHz

66 MHz

Units

Notes

Min.

Max.

Min.

Max.

Tclk2outb

Clock to output for all bused

signals. This is the PCI_AD[31:0],

PCI_CBE_N [3:0], PCI_PAR,

PCI_FRAME_N, PCI_IRDY_N,

PCI_TRDY_N, PCI_STOP_N,

PCI_DEVSEL_N, PCI_PERR_N,

PCI_SERR_N

211

1, 2, 5,

7, 8

Tclk2out

Clock to output for all point-to-point

signals. This is the PCI_GNT_N

and PCI_REQ_N(0) only.

2121

1, 2, 5,

7, 8

Tsetupb

Input setup time for all bused

signals. This is the PCI_AD[31:0],

PCI_CBE_N [3:0], PCI_PAR,

PCI_FRAME_N, PCI_IRDY_N,

PCI_TRDY_N, PCI_STOP_N,

PCI_DEVSEL_N, PCI_PERR_N,

PCI_SERR_N

4, 6, 7,

Tsetup

Input setup time for all

point-to-point signals. This is the

PCI_REQ_N and PCI_GNT_N(0)

only.

10, 12

4, 7, 8

Thold

Input hold time from clock.

4, 7, 8

Trst-off

Reset active-to-output float delay

5, 6, 7,

PRIXP425BD датащи(PDF) 88 Page - Intel Corporation

PRIXP425BD датащи(HTML) 88 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL