PRIXP425BD datasheet(36/112 Pages) INTEL

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Intel® IXP42X Product Line and IXC1100 Control Plane Processor

Functional Signal Descriptions

Datasheet

ETH_RXDATA0[3:0]

ZVI

Receive data bus from PHY, data sampled synchronously with respect

to ETH_RXCLK0

• Should be pulled low through a 10-K

Ω resistor when not being

utilized in the system.

ETH_RXDV0

ZVI

Receive data valid, used to inform the MII interface that the Ethernet

PHY is sending data. Should be pulled low through a 10-K

Ω resistor

when not being utilized in the system.

ETH_COL0

ZVI

Asserted by the PHY when a collision is detected by the PHY. Should be

pulled low through a 10-K

Ω resistor when not being utilized in the

system.

ETH_CRS0

ZVI

Asserted by the PHY when the transmit medium or receive medium is

active. De-asserted when both the transmit and receive medium are

idle. Remains asserted throughout the duration of a collision condition.

PHY asserts CRS asynchronously and de-asserts synchronously, with

respect to ETH_RXCLK0. Should be pulled low through a 10-K

Ω resistor

when not being utilized in the system.

ETH_MDIO

I/O

Management data output. Provides the write data to both PHY devices

connected to each MII interface.

Should be pulled low through a 10-K

Ω resistor when not being utilized in

the system.

ETH_MDC

Management data clock. Management data interface clock is used to

clock the MDIO signal as an output and sample the MDIO as an input.

The ETH_MDC is an input on power up and can be configured to be an

output through an Intel API as documented in the Intel® IXP400

Software Programmer’s Guide.

ETH_TXCLK1

ZVI

Externally supplied transmit clock.

• 25 MHz for 100-Mbps operation

• 2.5 MHz for 10 Mbps

Should be pulled low through a 10-K

Ω resistor when not being utilized in

the system.

ETH_TXDATA1[3:0]

Transmit data bus to PHY, asserted synchronously with respect to

ETH_TXCLK1.

ETH_TXEN1

Indicates that the PHY is being presented with nibbles on the MII

interface. Asserted synchronously, with respect to ETH_TXCLK1, at the

first nibble of the preamble, and remains asserted until all the nibbles of

a frame are presented.

ETH_RXCLK1

ZVI

Externally supplied receive clock.

• 25 MHz for 100-Mbps operation

• 2.5 MHz for 10 Mbps

Should be pulled low through a 10-K

Ω resistor when not being utilized in the

system.

ETH_RXDATA1[3:0]

ZVI

Receive data bus from PHY, data sampled synchronously, with respect

to ETH_RXCLK1.

• Should be pulled low through a 10-K

Ω resistor when not being

utilized in the system.

ETH_RXDV1

ZVI

Receive data valid, used to inform the MII interface that the Ethernet

PHY is sending data.

Should be pulled low through a 10-K

Ω resistor when not being utilized in

the system.

ETH_COL1

ZVI

Asserted by the PHY when a collision is detected by the PHY.

• Should be pulled low through a 10-K

Ω resistor when not being

utilized in the system.

ETH_CRS1

ZVI

Asserted by the PHY when the transmit medium or receive medium are

active. De-asserted when both the transmit and receive medium are

idle. Remains asserted throughout the duration of collision condition.

PHY asserts CRS asynchronously and de-asserts synchronously with

respect to ETH_RXCLK1.

Should be pulled low through a 10-K

Ω resistor when not being utilized in

the system.

Table 9.

MII Interfaces (Sheet 2 of 2)

Name

Power

Reset†

Reset† Type†

Description

†

For a legend of the Type codes, see Table 4 on page 30.

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