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APA600 датащи(PDF) 63 Page - Actel Corporation |
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APA600 датащи(HTML) 63 Page - Actel Corporation |
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63 / 178 page ![]() ProASICPLUS Flash Family FPGAs v5.9 2-53 Table 2-50 • JTAG Switching Characteristics Description Symbol Min Max Unit Output delay from TCK falling to TDI, TMS tTCKTDI –4 4 ns TDO Setup time before TCK rising tTDOTCK 10 ns TDO Hold time after TCK rising tTCKTDO 0 ns TCK period tTCK 100 2 1,000 ns RCK period tRCK 100 1,000 ns Notes: 1. For DC electrical specifications of the JTAG pins (TCK, TDI, TMS, TDO, TRST), refer to Table 2-22 on page 2-34 when VDDP = 2.5 V and Table 2-24 on page 2-38 when VDDP = 3.3 V. 2. If RCK is being used, there is no minimum on the TCK period. Figure 2-27 • JTAG Operation Timing TCK TMS, TDI TDO tTCK tTCKTDI tTCKTDO tTDOTCK |
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