APA600 datasheet(80/178 Pages) ACTEL

80 / 178 page

ProASICPLUS Flash Family FPGAs

2- 70

v5.9

Synchronous FIFO Read, Pipeline Mode Outputs (Synchronous Pipelined)

Note: The plot shows the normal operation status.

Figure 2-43 • Synchronous FIFO Read, Pipeline Mode Outputs (Synchronous Pipelined)

Table 2-66 • TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/Industrial

TJ = –55°C to 150°C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883

Symbol txxx

Description

Min.

Max.

Units

Notes

CCYC

Cycle time

7.5

CMH

Clock high phase

3.0

CML

Clock low phase

3.0

ECBA

New EMPTY access from RCLKS

↓

3.0*

FCBA

FULL

↓ access from RCLKS ↓

3.0*

ECBH, FCBH,

THCBH

Old EMPTY, FULL, EQTH, & GETH valid hold

time from RCLKS

↓

1.0

Empty/full/thresh are invalid from the end of

hold until the new access is complete

OCA

New DO access from RCLKS

↑

2.0

OCH

Old DO valid from RCLKS

↑

0.75

RDCH

RDB hold from RCLKS

↑

0.5

RDCS

RDB setup to RCLKS

↑

1.0

RPCA

New RPE access from RCLKS

↑

4.0

RPCH

Old RPE valid from RCLKS

↑

1.0

HCBA

EQTH or GETH access from RCLKS

↓

4.5

Note: *At fast cycles, ECBA and FCBA = MAX (7.5 ns – CMS), 3.0 ns.

RCLK

RPE

RDATA

EMPTY

EQTH, GETH

FULL

Old Data Out

New Valid Data Out

RDB

Cycle Start

Old RPE Out

New RPE Out

tECBH, tFCBH

tRDCH

tRDCS

tOCA

tECBA, tFCBA

tTHCBH

tHCBA

tCMH

tCML

tCCYC

tRPCH

tOCH

tRPCA

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