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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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APA600 датащи(PDF) 78 Page - Actel Corporation |
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APA600 датащи(HTML) 78 Page - Actel Corporation |
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78 / 178 page  ProASICPLUS Flash Family FPGAs 2- 68 v5.9 Asynchronous FIFO Write Note: The plot shows the normal operation status. Figure 2-41 • Asynchronous FIFO Write Table 2-64 • TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/Industrial TJ = –55°C to 150°C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883 Symbol txxx Description Min. Max. Units Notes DWRH DI hold from WB ↑ 1.5 ns DWRS DI setup to WB ↑ 0.5 ns PARGEN is inactive DWRS DI setup to WB ↑ 2.5 ns PARGEN is active EWRH, FWRH, THWRH Old EMPTY, FULL, EQTH, & GETH valid hold time after WB ↑ 0.5 ns Empty/full/thresh are invalid from the end of hold until the new access is complete EWRA EMPTY ↓ access from WB ↑ 3.01 ns FWRA New FULL access from WB ↑ 3.01 ns THWRA EQTH or GETH access from WB ↑ 4.5 ns WPDA WPE access from DI 3.0 ns WPE is invalid while PARGEN is active WPDH WPE hold from DI 1.0 ns WRCYC Cycle time 7.5 ns WRRDS RB ↑, clearing FULL, setup to WB ↓ 3.02 ns Enabling the write operation 1.0 Inhibiting the write operation WRH WB high phase 3.0 ns Inactive WRL WB low phase 3.0 ns Active Notes: 1. At fast cycles, EWRA, FWRA = MAX (7.5 ns – WRL), 3.0 ns. 2. At fast cycles, WRRDS (for enabling write) = MAX (7.5 ns – RDL), 3.0 ns. 3. After FIFO reset, WRB needs an initial falling edge prior to any write actions. WPE WDATA (Full inhibits write) WB = (WRB + WBLKB) EMPTY EQTH, GETH FULL Cycle Start RB tWRRDS tDWRH tWPDH tWPDA tDWRS tEWRH, tFWRH tEWRA, tFWRA tTHWRH tTHWRA tWRH tWRL tWRCYC |
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