APA600 datasheet(56/178 Pages) ACTEL

номер детали	APA600

подробное описание детали	ProASICPLUS짰 Flash Family FPGAs

PDF	178 Pages

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производитель	ACTEL [Actel Corporation]

домашняя страница	http://www.actel.com

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ProASICPLUS Flash Family FPGAs

2- 46

v5.9

Input Buffer Delays

Figure 2-25 • Input Buffer Delays

Table 2-35 • Worst-Case Commercial Conditions

VDDP = 3.0 V, VDD = 2.3 V, TJ = 70°C

Macro Type

Description

Max. tINYH

Max. tINYL

Units

Std.

IB33

3.3 V, CMOS Input Levels3, No Pull-up Resistor

0.4

0.6

IB33S

3.3 V, CMOS Input Levels3, No Pull-up Resistor, Schmitt Trigger

0.6

0.8

Notes:

1. tINYH = Input Pad-to-Y High

2. tINYL = Input Pad-to-Y Low

3. LVTTL delays are the same as CMOS delays.

4. For LP Macros, VDDP=2.3 V for delays.

Table 2-36 • Worst-Case Commercial Conditions

VDDP = 2.3 V, VDD = 2.3 V, TJ = 70°C

Macro Type

Description

Max. tINYH

Max. tINYL

Units

Std.

IB25LP

2.5 V, CMOS Input Levels3, Low Power

0.9

0.6

IB25LPS

2.5 V, CMOS Input Levels3, Low Power, Schmitt Trigger

0.7

0.9

Notes:

1. tINYH = Input Pad-to-Y High

2. tINYL = Input Pad-to-Y Low

3. LVTTL delays are the same as CMOS delays.

4. For LP Macros, VDDP =2.3 V for delays.

PAD

DDP

0 V

50%

GND

50%

INYH

50%

IBx

INYL

APA600 датащи(PDF) 56 Page - Actel Corporation

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