APA600 datasheet(79/178 Pages) ACTEL

79 / 178 page

ProASICPLUS Flash Family FPGAs

v5.9

2-69

Synchronous FIFO Read, Access Timed Output Strobe (Synchronous Transparent)

Note: The plot shows the normal operation status.

Figure 2-42 • Synchronous FIFO Read, Access Timed Output Strobe (Synchronous Transparent)

Table 2-65 • TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/Industrial

TJ = –55°C to 150°C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883

Symbol txxx

Description

Min.

Max.

Units

Notes

CCYC

Cycle time

7.5

CMH

Clock high phase

3.0

CML

Clock low phase

3.0

ECBA

New EMPTY access from RCLKS

↓

3.0*

FCBA

FULL

↓ access from RCLKS ↓

3.0*

ECBH,

FCBH,

THCBH

Old EMPTY, FULL, EQTH, & GETH valid hold

time from RCLKS

↓

1.0

Empty/full/thresh are invalid from the end

of hold until the new access is complete

OCA

New DO access from RCLKS

↑

7.5

OCH

Old DO valid from RCLKS

↑

3.0

RDCH

RDB hold from RCLKS

↑

0.5

RDCS

RDB setup to RCLKS

↑

1.0

RPCA

New RPE access from RCLKS

↑

9.5

RPCH

Old RPE valid from RCLKS

↑

3.0

HCBA

EQTH or GETH access from RCLKS

↓

4.5

Note: *At fast cycles, ECBA and FCBA = MAX (7.5 ns – CMH), 3.0 ns.

RCLK

RPE

RDATA

EMPTY

EQTH, GETH

FULL

RDB

tRDCH

tOCH

tRPCH

tRDCS

OldDataOut

New Valid Data Out (Empty Inhibits Read)

Cycle Start

tECBH, tFCBH

tECBA, tFCBA

tOCA

tRPCA

tCMH

tCML

tCCYC

tTHCBH

tHCBA

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