APA600 datasheet(83/178 Pages) ACTEL

83 / 178 page

ProASICPLUS Flash Family FPGAs

v5.9

2-73

Pin Description

User Pins

I/O

User Input/Output

The I/O pin functions as an input, output, tristate, or

bidirectional buffer. Input and output signal levels are

compatible

with

standard

LVTTL

and

LVCMOS

specifications. Unused I/O pins are configured as inputs

with pull-up resistors.

No Connect

To maintain compatibility with other Actel ProASICPLUS

products, it is recommended that this pin not be

connected to the circuitry on the board.

Global Pin

Low skew input pin for clock or other global signals. This

pin can be configured with an internal pull-up resistor.

When it is not connected to the global network or the

clock conditioning circuit, it can be configured and used

as a normal I/O.

GLMX

Global Multiplexing Pin

Low skew input pin for clock or other global signals. This

pin can be used in one of two special ways (refer to

Actel’s Using ProASICPLUS Clock Conditioning Circuits).

When the external feedback option is selected for the

PLL block, this pin is routed as the external feedback

source to the clock conditioning circuit.

In applications where two different signals access the

same global net at different times through the use of

GLMXx and GLMXLx macros, this pin will be fixed as one

of the source pins.

This pin can be configured with an internal pull-up

resistor. When it is not connected to the global network

or the clock conditioning circuit, it can be configured and

used as any normal I/O. If not used, the GLMXx pin will

be configured as an input with pull-up.

Dedicated Pins

GND

Ground

Common ground supply voltage.

VDD

Logic Array Power Supply Pin

2.5 V supply voltage.

VDDP

I/O Pad Power Supply Pin

2.5 V or 3.3 V supply voltage.

TMS

Test Mode Select

The TMS pin controls the use of boundary-scan circuitry.

This pin has an internal pull-up resistor.

TCK

Test Clock

Clock input pin for boundary scan (maximum 10 MHz). Actel

recommends adding a nominal 20 k

Ω pull-up resistor to this

pin.

TDI

Test Data In

Serial input for boundary scan. A dedicated pull-up

resistor is included to pull this pin high when not being

driven.

TDO

Test Data Out

Serial output for boundary scan. Actel recommends

adding a nominal 20k

Ω pull-up resistor to this pin.

TRST

Test Reset Input

Asynchronous,

active

low

input pin

for

resetting

boundary-scan circuitry. This pin has an internal pull-up

resistor. For more information, please refer to Power-up

Behavior of ProASICPLUS Devices application note.

Special Function Pins

RCK

Running Clock

A free running clock is needed during programming if

the programmer cannot guarantee that TCK will be

uninterrupted. If not used, this pin has an internal pull-

up and can be left floating.

NPECL

User Negative Input

Provides high speed clock or data signals to the PLL

block. If unused, leave the pin unconnected.

PPECL

User Positive Input

Provides high speed clock or data signals to the PLL

block. If unused, leave the pin unconnected.

AVDD

PLL Power Supply

Analog VDD should be VDD (core voltage) 2.5 V (nominal)

and be decoupled from GND with suitable decoupling

capacitors to reduce noise. For more information, refer

to Actel’s Using ProASICPLUS Clock Conditioning Circuits

application note. If the clock conditioning circuitry is not

used in a design, AVDD can either be left floating or tied

to 2.5 V.

AGND

PLL Power Ground

The analog ground can be connected to the system

ground. For more information, refer to Actel’s Using

ProASICPLUS Clock Conditioning Circuits application note.

If the PLLs or clock conditioning circuitry are not used in

a design, AGND should be tied to GND.

APA600 датащи(PDF) 83 Page - Actel Corporation

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