APA600 datasheet(60/178 Pages) ACTEL

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ProASICPLUS Flash Family FPGAs

2- 50

v5.9

Predicted Global Routing Delay

Global Routing Skew

Table 2-43 • Worst-Case Commercial Conditions1

VDDP = 3.0 V, VDD = 2.3 V, TJ = 70°C

Parameter

Description

Max.

Units

Std.

tRCKH

Input Low to High2

1.1

tRCKL

Input High to Low2

1.0

tRCKH

Input Low to High3

0.8

tRCKL

Input High to Low3

0.8

Notes:

1. The timing delay difference between tile locations is less than 15 ps.

2. Highly loaded row 50%.

3. Minimally loaded row.

Table 2-44 • Worst-Case Military Conditions

VDDP = 3.0V, VDD = 2.3V, TJ = 125°C for Military/MIL-STD-883

Parameter

Description

Max.

Units

tRCKH

Input Low to High (high loaded row of 50%)

1.1

tRCKL

Input High to Low (high loaded row of 50%)

1.0

tRCKH

Input Low to High (minimally loaded row)

0.8

tRCKL

Input High to Low (minimally loaded row)

0.8

Note: * The timing delay difference between tile locations is less than 15 ps.

Table 2-45 • Worst-Case Commercial Conditions

VDDP = 3.0 V, VDD = 2.3 V, TJ = 70°C

Parameter

Description

Max.

Units

Std.

tRCKSWH

Maximum Skew Low to High

270

tRCKSHH

Maximum Skew High to Low

270

Table 2-46 • Worst-Case Commercial Conditions

VDDP = 3.0V, VDD = 2.3V, TJ = 125°C for Military/MIL-STD-883

Parameter

Description

Max.

Units

tRCKSWH

Maximum Skew Low to High

270

tRCKSHH

Maximum Skew High to Low

270

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