APA600 datasheet(61/178 Pages) ACTEL

номер детали	APA600

подробное описание детали	ProASICPLUS짰 Flash Family FPGAs

PDF	178 Pages

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производитель	ACTEL [Actel Corporation]

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ProASICPLUS Flash Family FPGAs

v5.9

2-51

Module Delays

Sample Macrocell Library Listing

Figure 2-26 • Module Delays

Table 2-47 • Worst-Case Military Conditions1

VDD = 2.3 V, TJ = 70º C, TJ = 70°C, TJ = 125°C for Military/MIL-STD-883

Cell Name

Description

Std.

Max

Min

Units

NAND2

2-Input NAND

0.5

AND2

2-Input AND

0.7

NOR3

3-Input NOR

0.8

MUX2L

2-1 MUX with Active Low Select

0.5

OA21

2-Input OR into a 2-Input AND

0.8

XOR2

2-Input Exclusive OR

0.6

LDL

Active Low Latch (LH/HL)

LH2

0.9

CLK-Q

HL2

0.8

tsetup

0.7

thold

0.1

DFFL

Negative Edge-Triggered D-type Flip-Flop (LH/HL)

CLK-Q

LH2

0.9

HL2

0.8

tsetup

0.6

thold

0.0

Notes:

1. Intrinsic delays have a variable component, coupled to the input slope of the signal. These numbers assume an input slope typical of

local interconnect.

2. LH and HL refer to the Q transitions from Low to High and High to Low, respectively.

50%

50% 50%

50%

50%50%

50%

DALH

DBLH

DAHL

DBHL

DCHL

DCLH

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