APA600 datasheet(38/178 Pages) ACTEL

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ProASICPLUS Flash Family FPGAs

2- 28

v5.9

Calculating Typical Power Dissipation

ProASICPLUS device power is calculated with both a static and an active component. The active component is a function

of both the number of tiles utilized and the system speed. Power dissipation can be calculated using the following

formula:

Total Power Consumption—Ptotal

Ptotal = Pdc + Pac

where:

Global Clock Contribution—Pclock

Pclock, the clock component of power dissipation, is given by the piece-wise model:

for R < 15000 the model is: (P1 + (P2*R) – (P7*R2)) * Fs (lightly-loaded clock trees)

for R > 15000 the model is: (P10 + P11*R) * Fs (heavily-loaded clock trees)

where:

Storage-Tile Contribution—Pstorage

Pstorage, the storage-tile (Register) component of AC power dissipation, is given by

Pstorage = P5 * ms * Fs

where:

Pdc =

7 mW for the APA075

8 mW for the APA150

11 mW for the APA300

12 mW for the APA450

12 mW for the APA600

13 mW for the APA750

19 mW for the APA1000

Pdc includes the static components of PVDDP + PVDD + PAVDD

Pac =Pclock + Pstorage + Plogic + Poutputs + Pinputs + Ppll + Pmemory

= 100 µW/MHz is the basic power consumption of the clock tree per MHz of the clock

= 1.3 µW/MHz is the incremental power consumption of the clock tree per storage tile – also per MHz of the

clock

= 0.00003 µW/MHz is a correction factor for partially-loaded clock trees

P10

= 6850 µW/MHz is the basic power consumption of the clock tree per MHz of the clock

P11

= 0.4 µW/MHz is the incremental power consumption of the clock tree per storage tile – also per MHz of

the clock

= the number of storage tiles clocked by this clock

= the clock frequency

1.1 µW/MHz is the average power consumption of a storage tile per MHz of its output toggling rate.

The maximum output toggling rate is Fs/2.

the number of storage tiles (Register) switching during each Fs cycle

the clock frequency

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