S25FS256S datasheet(19/154 Pages) SPANSION

19 / 154 page

November 6, 2013 S25FS-S_00_04

S25FS-S Family

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Shee t

(Prelim i nar y )

3.2

Multiple Input / Output (MIO)

Traditional SPI single bit wide commands (Single or SIO) send information from the host to the memory only

on the Serial Input (SI) signal. Data may be sent back to the host serially on the Serial Output (SO) signal.

Dual or Quad Input / Output (I/O) commands send instructions to the memory only on the SI/IO0 signal.

Address or data is sent from the host to the memory as bit pairs on IO0 and IO1 or four bit (nibble) groups on

IO0, IO1, IO2, and IO3. Data is returned to the host similarly as bit pairs on IO0 and IO1 or four bit (nibble)

groups on IO0, IO1, IO2, and IO3.

QPI Mode transfers all instructions, address, and data from the host to the memory as four bit (nibble) groups

on IO0, IO1, IO2, and IO3. Data is returned to the host similarly as four bit (nibble) groups on IO0, IO1, IO2,

and IO3.

3.3

Serial Clock (SCK)

This input signal provides the synchronization reference for the SPI interface. Instructions, addresses, or data

input are latched on the rising edge of the SCK signal. Data output changes after the falling edge of SCK, in

SDR commands, and after every edge in DDR commands.

3.4

Chip Select (CS#)

The Chip Select signal indicates when a command is transferring information to or from the device and the

other signals are relevant for the memory device.

When the CS# signal is at the logic high state, the device is not selected and all input signals are ignored and

all output signals are high impedance. The device will be in the Standby Power mode, unless an internal

embedded operation is in progress. An embedded operation is indicated by the Status Register 1

Write-In-Progress bit (SR1V[1]) set to 1, until the operation is completed. Some example embedded

operations are: Program, Erase, or Write Registers (WRR) operations.

Driving the CS# input to the logic low state enables the device, placing it in the Active Power mode. After

power-up, a falling edge on CS# is required prior to the start of any command.

3.5

Serial Input (SI) / IO0

This input signal is used to transfer data serially into the device. It receives instructions, addresses, and data

to be programmed. Values are latched on the rising edge of serial SCK clock signal.

SI becomes IO0 - an input and output during Dual and Quad commands for receiving instructions, addresses,

and data to be programmed (values latched on rising edge of serial SCK clock signal) as well as shifting out

data (on the falling edge of SCK, in SDR commands, and on every edge of SCK, in DDR commands).

3.6

Serial Output (SO) / IO1

This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of

the serial SCK clock signal.

SO becomes IO1 - an input and output during Dual and Quad commands for receiving addresses, and data to

be programmed (values latched on rising edge of serial SCK clock signal) as well as shifting out data (on the

falling edge of SCK, in SDR commands, and on every edge of SCK, in DDR commands).

3.7

Write Protect (WP#) / IO2

When WP# is driven Low (VIL), during a WRR or WRAR command and while the Status Register Write

Disable (SRWD_NV) bit of Status Register 1 (SR1NV[7]) is set to a 1, it is not possible to write to Status

WRAR command selecting SR1NV, SR1V, CR1NV, or CR1V is ignored, and no error is set.

This prevents any alteration of the Block Protection settings. As a consequence, all the data bytes in the

memory area that are protected by the Block Protection feature are also hardware protected against data

modification if WP# is Low during a WRR or WRAR command with SRWD_NV set to 1.

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