S25FS256S datasheet(67/154 Pages) SPANSION

67 / 154 page

November 6, 2013 S25FS-S_00_04

S25FS-S Family

Da ta

Shee t

(Prelim i nar y )

Read Latency Non-Volatile CR2NV[3:0]: This bit controls the POR, hardware reset, or software reset state

of the Read Latency (dummy cycle) delay in all variable latency read commands. The following read

commands have a variable latency period between the end of address or mode and the beginning of read

data returning to the host:

 Fast Read

 Dual I/O Read

 Quad I/O Read

 DDR Quad I/O Read

 OTPR

 RDAR

This Non-Volatile Read Latency configuration bit sets the number of read latency (dummy cycles) in use so

the device can start immediately (boot) with an appropriate read latency for the host system.

Notes:

1. SCK frequency > 133 MHz SDR, or 80 MHz DDR is not supported by this family of devices.

2. The Dual I/O, Quad I/O, QPI, DDR Quad I/O, and DDR QPI, command protocols include Continuous Read mode bits following the

address. The clock cycles for these bits are not counted as part of the latency cycles shown in the table. Example: the legacy

Quad I/O command has 2 Continuous Read mode cycles following the address. Therefore, the legacy Quad I/O command without

additional read latency is supported only up to the frequency shown in the table for a read latency of 0 cycles. By increasing the variable

read latency the frequency of the Quad I/O command can be increased to allow operation up to the maximum supported 133 MHz

frequency.

3. Other read commands have fixed latency, e.g. Read always has zero read latency. RSFDP always has eight cycles of latency.

4. DDR QPI is only supported for Latency Cycles 1 through 5 and for clock frequency of up to 68 MHz.

Table 8.20 Latency Code (Cycles) Versus Frequency

Latency

Cycles

Read Command Maximum Frequency (MHz)

Fast Read (1-1-1)

OTPR (1-1-1)

RDAR (1-1-1)

RDAR (4-4-4)

Dual I/O (1-2-2)

Quad I/O (1-4-4)

QPI (4-4-4)

DDR Quad I/O (1-4-4)

DDR QPI (4-4-4) (Note 4)

Mode Cycles = 0

Mode Cycles = 4

Mode Cycles = 2

Mode Cycles = 1

508040

N/A

66925322

104

116

104

129

116

133

104

129

133

116

133

129

133

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