S25FS256S datasheet(65/154 Pages) SPANSION

65 / 154 page

November 6, 2013 S25FS-S_00_04

S25FS-S Family

Da ta

Shee t

(Prelim i nar y )

Freeze Protection (FREEZE) CR1V[0]: The Freeze bit, when set to 1, locks the current state of the Block

Protection control bits and OTP area:

 BPNV_2-0 bits in the non-volatile Status Register 1 (SR1NV[4:2])

 BP 2-0 bits in the volatile Status Register 1 (SR1V[4:2])

 TBPROT_O, TBPARM_O, and BPNV_O bits in the non-volatile Configuration Register (CR1NV[53, 2])

 TBPROT, TBPARM, and BPNV bits in the volatile Configuration Register (CR1V[5, 3, 2]) are indirectly

protected in that they are shadows of the related CR1NV OTP bits and are read only

 the entire OTP memory space

Any attempt to change the above listed bits while FREEZE = 1 is prevented:

 The WRR command does not affect the listed bits and no error status is set.

 The WRAR command does not affect the listed bits and no error status is set.

 The OTPP command, with an address within the OTP area, fails and the P-ERR status is set.

As long as the FREEZE bit remains cleared to logic 0 the Block Protection control bits and FREEZE are

writable, and the OTP address space is programmable.

Once the FREEZE bit has been written to a logic 1 it can only be cleared to a logic 0 by a power-off to power-

on cycle or a hardware reset. Software reset will not affect the state of the FREEZE bit.

The CR1V[0] FREEZE bit is volatile and the default state of FREEZE after power-on comes from FREEZE_D

in CR1NV[0]. The FREEZE bit can be set in parallel with updating other values in CR1V by a single WRR or

WRAR command.

The FREEZE bit does not prevent the WRR or WRAR commands from changing the SRWD_NV (SR1NV[7]),

Quad_NV (CR1NV[1]), or QUAD (CR1V[1]) bits.

S25FS256S датащи(PDF) 65 Page - SPANSION