S25FS256S datasheet(90/154 Pages) SPANSION

90 / 154 page

S25FS-S Family

S25FS-S_00_04 November 6, 2013

Data

Sheet

(Pre limin ar y)

10.1.4.1

Monitoring Operation Status

The host system can determine when a write, program, erase, suspend or other embedded operation is

complete by monitoring the Write-In-Progress (WIP) bit in the Status Register. The Read from

Status Register 1 command or Read Any Register command provides the state of the WIP bit. The program

error (P_ERR) and erase error (E_ERR) bits in the Status Register indicate whether the most recent program

or erase command has not completed successfully. When P_ERR or E_ERR bits are set to 1, the WIP bit will

remain set to one indicating the device remains busy and unable to receive most new operation commands.

Only Status Read (RDSR1 05h), Read Any Register (RDAR 65h), Status Clear (CLSR 30h or 82h), and

Software Reset (RSTEN 66h, RST 99h or RESET F0h) are valid commands when P_ERR or E_ERR is set to

1. A Clear Status Register (CLSR) followed by a Write Disable (WRDI) command must be sent to return the

device to standby state. Clear Status Register clears the WIP, P_ERR, and E_ERR bits. WRDI clears the

WEL bit. Alternatively, hardware reset, or software reset (RST or RESET) may be used to return the device to

standby state.

10.1.4.2

Configuration

There are commands to read, write, and protect registers that control interface path width, interface timing,

interface address length, and some aspects of data protection.

10.1.5

Read Flash Array

Data may be read from the memory starting at any byte boundary. Data bytes are sequentially read from

incrementally higher byte addresses until the host ends the data transfer by driving CS# input High. If the byte

address reaches the maximum address of the memory array, the read will continue at address zero of the

array.

There are several different read commands to specify different access latency and data path widths. Double

Data Rate (DDR) commands also define the address and data bit relationship to both SCK edges:

 The Read command provides a single address bit per SCK rising edge on the SI signal with read data

returning a single bit per SCK falling edge on the SO signal. This command has zero latency between the

address and the returning data but is limited to a maximum SCK rate of 50MHz.

 Other read commands have a latency period between the address and returning data but can operate at

higher SCK frequencies. The latency depends on a Configuration Register read latency value.

 The Fast Read command provides a single address bit per SCK rising edge on the SI signal with read data

returning a single bit per SCK falling edge on the SO signal.

 Dual or Quad I/O Read commands provide address two bits or four bits per SCK rising edge with read data

returning two bits, or four bits of data per SCK falling edge on the IO0-IO3 signals.

 Quad Double Data Rate read commands provide address four bits per every SCK edge with read data

returning four bits of data per every SCK edge on the IO0-IO3 signals.

10.1.6

Program Flash Array

Programming data requires two commands: Write Enable (WREN), and Page Program (PP). The Page

Program command accepts from 1 byte up to 256 or 512 consecutive bytes of data (page) to be programmed

in one operation. Programming means that bits can either be left at 1, or programmed from 1 to 0. Changing

bits from 0 to 1 requires an erase operation.

10.1.7

Erase Flash Array

The Parameter Sector Erase, Sector Erase, or Bulk Erase commands set all the bits in a sector or the entire

memory array to 1. A bit needs to be first erased to 1 before programming can change it to a 0. While bits can

be individually programmed from a 1 to 0, erasing bits from 0 to 1 must be done on a sector-wide or array-

wide (bulk) level. The Write Enable (WREN) command must precede an erase command.

S25FS256S датащи(PDF) 90 Page - SPANSION

S25FS256S датащи(HTML) 90 Page - SPANSION

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL