S25FS256S datasheet(39/154 Pages) SPANSION

39 / 154 page

November 6, 2013 S25FS-S_00_04

S25FS-S Family

Da ta

Shee t

(Prelim i nar y )

6.3.2

IO3 / RESET# Input Initiated Hardware (Warm) Reset

The IO3 / RESET# signal functions as the RESET# input when CS# is high for more than tCS time or when

Quad Mode is not enabled CR1V[1]=0. The IO3 / RESET# input has an internal pull-up to VDD and may be

left unconnected if Quad Mode is not used. The tCS delay after CS# goes high gives the memory or host

system time to drive IO3 high after its use as a Quad Mode I/O signal while CS# was low. The internal pull-up

to VDD will then hold IO3 / RESET# high until the host system begins driving IO3 / RESET#. The

IO3 / RESET# input is ignored while CS# remains high during tCS, to avoid an unintended Reset operation. If

CS# is driven low to start a new command, IO3 / RESET# is used as IO3.

When the device is not in Quad Mode or, when CS# is high, and IO3 / RESET# transitions from VIH to VIL

for > tRP, following tCS, the device will reset register states in the same manner as Power-On Reset but, does

not go through the full reset process that is performed during POR. The hardware reset process requires a

period of tRPH to complete. If the POR process did not complete correctly for any reason during power-up

(tPU), RESET# going low will initiate the full POR process instead of the hardware reset process and will

require tPU to complete the POR process.

The RESET command is independent of the state of IO3 / RESET#. If IO3 / RESET# is high or unconnected,

and the RESET instruction is issued, the device will perform software reset.

Additional IO3 RESET# Notes:

 IO3 / RESET# must be high for t

RS following tPU or tRPH, before going low again to initiate a hardware

reset.

 When IO3 / RESET# is driven low for at least a minimum period of time (t

RP), following tCS, the device

terminates any operation in progress, makes all outputs high impedance, and ignores all read/write

commands for the duration of tRPH. The device resets the interface to standby state.

 If Quad Mode and the IO3 / RESET# feature are enabled, the host system should not drive IO3 low during

tCS, to avoid driver contention on IO3. Immediately following commands that transfer data to the host in

Quad Mode, e.g. Quad I/O Read, the memory drives IO3 / Reset high during tCS, to avoid an unintended

Reset operation. Immediately following commands that transfer data to the memory in Quad Mode, e.g.

Page Program, the host system should drive IO3 / Reset high during tCS, to avoid an unintended Reset

operation.

 If Quad Mode is not enabled, and if CS# is low at the time IO3 / RESET# is asserted low, CS# must return

high during tRPH before it can be asserted low again after tRH.

Notes:

1. IO3 / RESET# Low is ignored during power-up (tPU). If Reset# is asserted during the end of tPU, the device will remain in the reset state

and tRH will determine when CS# may go Low.

2. If Quad Mode is enabled, IO3 / RESET# Low is ignored during tCS.

3. Sum of tRP and tRH must be equal to or greater than tRPH.

Figure 6.7 Hardware Reset when Quad Mode is Not Enabled and IO3 / Reset# is Enabled

Table 6.3 Hardware Reset Parameters

Parameter

Description

Limit

Time

Unit

tRS

Reset Setup - Prior Reset end and RESET# high before RESET# low

Min

tRPH

Reset Pulse Hold - RESET# low to CS# low

Min

µs

tRP

RESET# Pulse Width

Min

200

tRH

Reset Hold - RESET# high before CS# low

Min

IO3_RESET#

CS#

Any prior reset

tRS

tRP

tRH

tRPH

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