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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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S25FS256S датащи(PDF) 73 Page - SPANSION |
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S25FS256S датащи(HTML) 73 Page - SPANSION |
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73 / 154 page  November 6, 2013 S25FS-S_00_04 S25FS-S Family 73 Da ta Shee t (Prelim i nar y ) 8.6.7 ASP Register (ASPR) Related Commands: ASP Read (ASPRD 2Bh) and ASP Program (ASPP 2Fh), Read Any Register (RDAR 65h), Write Any Register (WRAR 71h). The ASP register is a 16-bit OTP memory location used to permanently configure the behavior of Advanced Sector Protection (ASP) features. ASPR does not have user programmable volatile bits, all defined bits are OTP. The default state of the ASPR bits are programmed by Spansion. Password Protection Mode Lock Bit (PWDMLB) ASPR[2]: When programmed to 0, the Password Protection mode is permanently selected. Persistent Protection Mode Lock Bit (PSTMLB) ASPR[1]: When programmed to 0, the Persistent Protection mode is permanently selected. PWDMLB (ASPR[2]) and PSTMLB (ASPR[1]) are mutually exclusive, only one may be programmed to 0. ASPR bits may only be programmed while ASPR[2:1] = 11b. Attempting to program ASPR bits when ASPR[2:1] is not = 11b will result in a programming error with P_ERR (SR1V[6]) set to 1. After the ASP protection mode is selected by programming ASPR[2:1] = 10b or 01b, the state of all ASPR bits are locked and permanently protected from further programming. Attempting to program ASPR[2:1] = 00b will result in a programming error with P_ERR (SR1V[6]) set to 1. Similarly, OTP configuration bits listed in the ASP Register description (ASP Register on page 81), may only be programmed while ASPR[2:1] = 11b. The OTP configuration must be selected before selecting the ASP protection mode. The OTP configuration bits are permanently protected from further change when the ASP protection mode is selected. Attempting to program these OTP configuration bits when ASPR[2:1] is not = 11b will result in a programming error with P_ERR (SR1V[6]) set to 1. The ASP protection mode should be selected during system configuration to ensure that a malicious program does not select an undesired protection mode at a later time. By locking all the protection configuration via the ASP mode selection, later alteration of the protection methods by malicious programs is prevented. Table 8.27 ASP Register (ASPR) Bits Field Name Function Type Default State Description 15 to 9 RFU Reserved OTP 1 Reserved for Future Use. 8 RFU Reserved OTP 1 Reserved for Future Use. 7 RFU Reserved OTP 1 Reserved for Future Use. 6 RFU Reserved OTP 1 Reserved for Future Use. 5 RFU Reserved OTP 1 Reserved for Future Use. 4 RFU Reserved RFU 1 Reserved for Future Use. 3 RFU Reserved RFU 1 Reserved for Future Use. 2 PWDMLB Password Protection Mode Lock Bit OTP 1 0 = Password Protection mode permanently enabled. 1 = Password Protection mode not permanently enabled. 1 PSTMLB Persistent Protection Mode Lock Bit OTP 1 0 = Persistent Protection mode permanently enabled. 1 = Persistent Protection mode not permanently enabled. 0 RFU Reserved RFU 1 Reserved for Future Use. |
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