S25FS256S datasheet(61/154 Pages) SPANSION

61 / 154 page

November 6, 2013 S25FS-S_00_04

S25FS-S Family

Da ta

Shee t

(Prelim i nar y )

8.6.1.2

Status Register 1 Volatile (SR1V)

Related Commands: Read Status Register (RDSR1 05h), Write Registers (WRR 01h), Write Enable (WREN

06h), Write Disable (WRDI 04h), Clear Status Register (CLSR 30h or 82h), Read Any Register (RDAR 65h),

Write Any Register (WRAR 71h). This is the register displayed by the RDSR1 command.

Status Register Write (SRWD) SR1V[7]: SRWD is a volatile copy of SR1NV[7]. This bit tracks any changes

to the non-volatile version of this bit.

Program Error (P_ERR) SR1V[6]: The Program Error bit is used as a program operation success or failure

indication. When the Program Error bit is set to a 1 it indicates that there was an error in the last program

operation. This bit will also be set when the user attempts to program within a protected main memory sector,

or program within a locked OTP region. When the Program Error bit is set to a 1 this bit can be cleared to 0

with the Clear Status Register (CLSR) command. This is a read-only bit and is not affected by the WRR or

WRAR commands.

Erase Error (E_ERR) SR1V[5]: The Erase Error bit is used as an Erase operation success or failure

indication. When the Erase Error bit is set to a 1 it indicates that there was an error in the last erase operation.

This bit will also be set when the user attempts to erase an individual protected main memory sector. The

Bulk Erase command will not set E_ERR if a protected sector is found during the command execution. When

the Erase Error bit is set to a 1 this bit can be cleared to 0 with the Clear Status Register (CLSR) command.

This is a read-only bit and is not affected by the WRR or WRAR commands.

Block Protection (BP2, BP1, BP0) SR1V[4:2]: These bits define the main flash array area to be software

protected against program and Erase commands. The BP bits are selected as either volatile or non-volatile,

depending on the state of the BP non-volatile bit (BPNV_O) in the Configuration Register CR1NV[3]. When

CR1NV[3]=0 the non-volatile version of the BP bits (SR1NV[4:2]) are used to control Block Protection and the

WRR command writes SR1NV[4:2] and updates SR1V[4:2] to the same value. When CR1NV[3]=1 the volatile

version of the BP bits (SR1V[4:2]) are used to control Block Protection and the WRR command writes

SR1V[4:2] and does not affect SR1NV[4:2]. When one or more of the BP bits is set to 1, the relevant memory

area is protected against program and erase. The Bulk Erase (BE) command can be executed only when the

BP bits are cleared to 0’s. See Section 9.3, Block Protection on page 77 for a description of how the BP bit

values select the memory array area protected.

Table 8.15 Status Register 1 Volatile (SR1V)

Bits

Field

Name

Function

Type

Default State

Description

SRWD

Status Register

Write Disable

Volatile

Read Only

SR1NV

Volatile copy of SR1NV[7].

P_ERR

Programming

Error Occurred

Volatile

Read Only

1 = Error occurred.

0 = No Error.

E_ERR

Erase Error

Occurred

Volatile

Read Only

1= Error occurred.

0 = No Error.

BP2

Block

Protection

Volatile

Protects selected range of sectors (Block) from Program

or Erase when the BP bits are configured as volatile

(CR1NV[3]=1). Volatile copy of SR1NV[4:2] when BP

bits are configured as non-volatile. User writable when

BP bits are configured as volatile.

BP1

BP0

WEL

Write Enable

Latch

Volatile

1 = Device accepts Write Registers (WRR and WRAR),

Program, or Erase commands.

0 = Device ignores Write Registers (WRR and WRAR),

Program, or Erase commands.

This bit is not affected by WRR or WRAR, only WREN

and WRDI commands affect this bit.

WIP

Write-In-

Progress

Volatile

Read Only

1= Device Busy, an embedded operation is in progress

such as Program or Erase.

0 = Ready Device is in Standby mode and can accept

commands.

This bit is not affected by WRR or WRAR, it only

provides WIP status.

S25FS256S датащи(PDF) 61 Page - SPANSION

S25FS256S датащи(HTML) 61 Page - SPANSION

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL